Tuesday, 2021-04-13

lkclChips4Makers: iopadiovss.ap (and friends) are missing, Jean-Paul is going to take a look at the BigVia thing, he says it's likely to be a FreePDK options misconfiguration13:51
Chips4MakersBTW, I updated the FreePDK45 files to latest version of c4m-flexcell, so it may be solved.13:54
Chips4Makerslkcl: You don't need the .ap files for the IO cells, you do need `LibreSOCIO.setup()' in coriolis2/settings.py as this will initialize the Hurricane LibreSOCIO library.14:30
lkclChips4Makers: https://ftp.libre-soc.org/nohup.out214:48
lkclon soclayout experiments10_verilog/freepdk_c4m4514:49
lkcl*** mbk error *** alcloadphfig : unable to open file : iopadiovss.ap .14:49
lkclLibreSOCIO.setup() is in the coriolis2/settings.py14:50
lkclwhile JP's sorting out BigVia i'll do the boundary scan, using the pinmux info (dut pin names)15:35
lkclChips4Makers, i got slightly confused by the boundary scan test using the internal names (dut.ti.*core/pad*)17:49
lkclthat's how oe can be checked17:50
lkclbut for the "real" ASIC the oe signals aren't going to be available17:50
Chips4MakersOn a real ASIC you can test if the output pad is high impedance of oe is low, but likely I will just check that you can proper 0 and 1 outputs.18:23
lkclah yeah of course18:24
lkcli'm just thinking, should i spend the time doing "completely external" (ls180 pin names, excluding oe) boundary scan18:25
Chips4MakersI don't think this has priority; main reason why I wanted boundary scan is to be sure synthesis did not mess up the boundary scan shift register.18:26
Chips4MakersI think it is now more important if you can see if Coriolis P&R does introduce possible problems as that will need bug fixing by JP.18:31
Chips4MakersMy SRAM validiation now shows I have some fixing to do in the SRAM block.18:31
lkclChips4Makers: so i am running into different issues with P&R VST extraction19:00
lkcl* using niolib, the definition of gpio uses a bi-directional port and std_ulogic for the pinpad: this does not match with the VST file (which uses "linkage mux bit" which causes a syntax error)19:01
lkclreplacing that with "inout std_logic" causes a knock-on cascade that results in the gpio pad being the wrong port direction19:02
lkcli therefore shelved that temporarily and moved to FreePDK19:02
lkclwhereupon, in order to complete the P&R, the extraction of netlist for generating corona_cts_r.vst *requires* ap files in order to extract the netlist19:03
lkcl... and iopadiovss.ap is missing19:03
lkclso i am stuck if niolib is used19:04
lkcland stuck if FreePDK45 is used19:04
lkclone potential solution is to P&R without the corona / chip19:05
lkclgood to know about finding errors in the SRAM19:06
Chips4MakersI would not call it good...19:37
lkclat least you know!19:43
lkclHA! i got core2chip.py to generate the right thing, pre P&R works on the experiments10 add test19:57

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