| lkcl | Chips4Makers: iopadiovss.ap (and friends) are missing, Jean-Paul is going to take a look at the BigVia thing, he says it's likely to be a FreePDK options misconfiguration | 13:51 |
|---|---|---|
| Chips4Makers | BTW, I updated the FreePDK45 files to latest version of c4m-flexcell, so it may be solved. | 13:54 |
| Chips4Makers | lkcl: You don't need the .ap files for the IO cells, you do need `LibreSOCIO.setup()' in coriolis2/settings.py as this will initialize the Hurricane LibreSOCIO library. | 14:30 |
| lkcl | Chips4Makers: https://ftp.libre-soc.org/nohup.out2 | 14:48 |
| lkcl | on soclayout experiments10_verilog/freepdk_c4m45 | 14:49 |
| lkcl | ./build_full.sh | 14:49 |
| lkcl | *** mbk error *** alcloadphfig : unable to open file : iopadiovss.ap . | 14:49 |
| lkcl | LibreSOCIO.setup() is in the coriolis2/settings.py | 14:50 |
| lkcl | https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments10_verilog/freepdk_c4m45/coriolis2/settings.py;hb=HEAD#l27 | 14:51 |
| lkcl | while JP's sorting out BigVia i'll do the boundary scan, using the pinmux info (dut pin names) | 15:35 |
| lkcl | Chips4Makers, i got slightly confused by the boundary scan test using the internal names (dut.ti.*core/pad*) | 17:49 |
| lkcl | that's how oe can be checked | 17:50 |
| lkcl | but for the "real" ASIC the oe signals aren't going to be available | 17:50 |
| Chips4Makers | On a real ASIC you can test if the output pad is high impedance of oe is low, but likely I will just check that you can proper 0 and 1 outputs. | 18:23 |
| lkcl | ah yeah of course | 18:24 |
| lkcl | i'm just thinking, should i spend the time doing "completely external" (ls180 pin names, excluding oe) boundary scan | 18:25 |
| Chips4Makers | I don't think this has priority; main reason why I wanted boundary scan is to be sure synthesis did not mess up the boundary scan shift register. | 18:26 |
| Chips4Makers | I think it is now more important if you can see if Coriolis P&R does introduce possible problems as that will need bug fixing by JP. | 18:31 |
| Chips4Makers | My SRAM validiation now shows I have some fixing to do in the SRAM block. | 18:31 |
| lkcl | Chips4Makers: so i am running into different issues with P&R VST extraction | 19:00 |
| lkcl | * using niolib, the definition of gpio uses a bi-directional port and std_ulogic for the pinpad: this does not match with the VST file (which uses "linkage mux bit" which causes a syntax error) | 19:01 |
| lkcl | replacing that with "inout std_logic" causes a knock-on cascade that results in the gpio pad being the wrong port direction | 19:02 |
| lkcl | i therefore shelved that temporarily and moved to FreePDK | 19:02 |
| lkcl | whereupon, in order to complete the P&R, the extraction of netlist for generating corona_cts_r.vst *requires* ap files in order to extract the netlist | 19:03 |
| lkcl | ... and iopadiovss.ap is missing | 19:03 |
| lkcl | so i am stuck if niolib is used | 19:04 |
| lkcl | and stuck if FreePDK45 is used | 19:04 |
| lkcl | one potential solution is to P&R without the corona / chip | 19:05 |
| lkcl | (temporary) | 19:05 |
| lkcl | good to know about finding errors in the SRAM | 19:06 |
| Chips4Makers | I would not call it good... | 19:37 |
| lkcl | at least you know! | 19:43 |
| lkcl | HA! i got core2chip.py to generate the right thing, pre P&R works on the experiments10 add test | 19:57 |
| lkcl | HA | 19:57 |
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