| lkcl | Chips4Makers: niolib post-pnr cocotb sim for the simple experiments10_verilog add example works | 11:12 |
|---|---|---|
| Chips4Makers | lkcl: Sounds very promising. | 12:21 |
| lkcl | Chips4Makers, boundary scan also works | 12:36 |
| lkcl | it's hard-coded to connect to dut.corona.core.subckt_22_jtag | 12:37 |
| lkcl | sigh | 12:37 |
| lkcl | with the small tests (experiments10_verilog) it only takes a couple of minutes iteration (not 12 hours) | 12:38 |
| Chips4Makers | lkcl: We likely need a little bit bigger experiment also to stress test the HFNS and clock tree synthesis more. | 12:47 |
| lkcl | agreed. i'm thinking of doing a 2nd experiment to be able to add a wishbone interface | 12:49 |
| lkcl | and a DMI interface | 12:49 |
| lkcl | Chips4Makers, good call about HFNS testing | 20:28 |
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