Wednesday, 2021-04-14

lkclChips4Makers: niolib post-pnr cocotb sim for the simple experiments10_verilog add example works11:12
Chips4Makerslkcl: Sounds very promising.12:21
lkclChips4Makers, boundary scan also works12:36
lkclit's hard-coded to connect to dut.corona.core.subckt_22_jtag12:37
lkclwith the small tests (experiments10_verilog) it only takes a couple of minutes iteration (not 12 hours)12:38
Chips4Makerslkcl: We likely need a little bit bigger experiment also to stress test the HFNS and clock tree synthesis more.12:47
lkclagreed. i'm thinking of doing a 2nd experiment to be able to add a wishbone interface12:49
lkcland a DMI interface12:49
lkclChips4Makers, good call about HFNS testing20:28

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