| lkcl | Chips4Makers, VERSA_ECP5 FPGA jtag tap interface over 4 GPIO pins (i.e. not via the FT232 connected to the *FPGA's* JTAG port) confirmed working | 15:10 |
|---|---|---|
| lkcl | at least, it responded with an idscan | 15:10 |
| Chips4Makers | Vvvery good. | 15:28 |
| lkcl | using an FT232 dongle in bit-banging mode at only 5kbaud it "worked", yet it still caused the other USB-UART to go offline :) | 15:45 |
| Chips4Makers | When I test the Retro-uC on FPGA I typically mapped the JTAG pins to PMOD header. I then used a buspirate with OpenOCD to access the JTAG interface. It should work with any hardware device for which there is an OpenOCD driver. | 19:57 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!