Friday, 2021-04-16

lkclChips4Makers: cocotb-ghdl tests now pass with the "basic" experiment10, with HFNS enabled13:34
lkclthere is one thing, however: i corrected the wishbone unit test based on the results and it was back to what you have in c4m-jtag tests13:35
lkclthe pre-coriolis2 one (with ls180 and litex) *fails*13:36
lkclthis is i think because litex bus-paths introduces delays into responding13:36
lkclwhere the "simple" tests do not13:36
lkclbottom line, i suspect that c4m-jtag wishbone is not compliant14:02
lkcli had to fix one thing already (related to if stall is not available)14:02
Chips4Makerslkcl: At what frequency are you running clk and JTAG clock. JTAG clock frequency has to be lower (half or even lower) than main clock frequency. JTAG does not allow to put wait states so you have to be sure that the data can be read/written on the Wishbone bud before you try to access it from JTAG.15:20
Chips4MakersI also assumed that the Wishbone master was using the pipelined (e.g. Rev4) Wishbone. You added possibility to specify features for the Wishbone bus so the problem could be there.15:25
Chips4MakersActually nmigen-soc Wishbone should do the right thing if you connect a master with stall to a slave without stall, that's why I did not provide configurability in the Wishbone interface you add to the JTAG. Less code to test.15:35
lkclChips4Makers: long story17:02
lkcl1) setup_jtag was missing get_sim_steps(), without which the simulations of jtag clk were running 1,000,000 times faster than sys_clk17:03
lkcl2) the litex wishbone code when meshing a 64-bit bus to a 32-bit one has to have STB asserted for much longer.17:04
lkclSTB was being *deasserted* too early - before the ack had been sent - because it was in the middle of writing the first 32-bits and was about to run the upper 32-bits17:05
lkclbut jtag-c4m *deasserted* STB before it had a chance to do that17:06
lkcli "fixed" that by changing the c4m-jtag bus to 32-bit17:06
lkclthis also reduced the amount of gates by removing one of the internal litex bus-matching arbiters17:06
lkcleven when i did that it was still not working, hence why i put in the modification to assert stb during the extra states17:07
lkclit is still this:17:08
lkcl    clk_period = 100 # 10MHz17:08
lkcl    tck_period = 300 # 3MHz17:08
Chips4MakersThis is consequence of pipelined vs non-pipelined operation, as said properly handled by nmigen-soc wishbone implementation.17:08
lkcl  COCOTB_HDL_TIMEUNIT=100ps17:08
lkclexcept we're not using nmigen-soc wishbone implementation17:08
lkcli don't believe the litex code properly supports pipelining17:09
lkcloink.  verilator is actually managing to *delete* the JTAG FSMs (!)18:24
lkcleurrrrgh, migen is outputting verilog that's no longer compatible with the latest version of verilator18:32
lkclwait... err... no this is nmigen!18:44
lkclChips4Makers, found the problem - just as stb was not being asserted for long enough, neither was wen23:31
lkcljust checking now: cocotb-verilator (pre-coriolis2) is now "not freezing ridiculously"23:32
lkcland it works23:38

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