| lkcl | Chips4Makers: cocotb-ghdl tests now pass with the "basic" experiment10, with HFNS enabled | 13:34 |
|---|---|---|
| lkcl | there is one thing, however: i corrected the wishbone unit test based on the results and it was back to what you have in c4m-jtag tests | 13:35 |
| lkcl | BUT | 13:35 |
| lkcl | the pre-coriolis2 one (with ls180 and litex) *fails* | 13:36 |
| lkcl | this is i think because litex bus-paths introduces delays into responding | 13:36 |
| lkcl | where the "simple" tests do not | 13:36 |
| lkcl | bottom line, i suspect that c4m-jtag wishbone is not compliant | 14:02 |
| lkcl | i had to fix one thing already (related to if stall is not available) | 14:02 |
| Chips4Makers | lkcl: At what frequency are you running clk and JTAG clock. JTAG clock frequency has to be lower (half or even lower) than main clock frequency. JTAG does not allow to put wait states so you have to be sure that the data can be read/written on the Wishbone bud before you try to access it from JTAG. | 15:20 |
| Chips4Makers | I also assumed that the Wishbone master was using the pipelined (e.g. Rev4) Wishbone. You added possibility to specify features for the Wishbone bus so the problem could be there. | 15:25 |
| Chips4Makers | Actually nmigen-soc Wishbone should do the right thing if you connect a master with stall to a slave without stall, that's why I did not provide configurability in the Wishbone interface you add to the JTAG. Less code to test. | 15:35 |
| lkcl | Chips4Makers: long story | 17:02 |
| lkcl | 1) setup_jtag was missing get_sim_steps(), without which the simulations of jtag clk were running 1,000,000 times faster than sys_clk | 17:03 |
| Chips4Makers | :) | 17:04 |
| lkcl | 2) the litex wishbone code when meshing a 64-bit bus to a 32-bit one has to have STB asserted for much longer. | 17:04 |
| lkcl | STB was being *deasserted* too early - before the ack had been sent - because it was in the middle of writing the first 32-bits and was about to run the upper 32-bits | 17:05 |
| lkcl | but jtag-c4m *deasserted* STB before it had a chance to do that | 17:06 |
| lkcl | i "fixed" that by changing the c4m-jtag bus to 32-bit | 17:06 |
| lkcl | this also reduced the amount of gates by removing one of the internal litex bus-matching arbiters | 17:06 |
| lkcl | even when i did that it was still not working, hence why i put in the modification to assert stb during the extra states | 17:07 |
| lkcl | it is still this: | 17:08 |
| lkcl | clk_period = 100 # 10MHz | 17:08 |
| lkcl | tck_period = 300 # 3MHz | 17:08 |
| Chips4Makers | This is consequence of pipelined vs non-pipelined operation, as said properly handled by nmigen-soc wishbone implementation. | 17:08 |
| lkcl | COCOTB_HDL_TIMEUNIT=100ps | 17:08 |
| lkcl | except we're not using nmigen-soc wishbone implementation | 17:08 |
| lkcl | i don't believe the litex code properly supports pipelining | 17:09 |
| lkcl | oink. verilator is actually managing to *delete* the JTAG FSMs (!) | 18:24 |
| lkcl | wtf | 18:24 |
| lkcl | eurrrrgh, migen is outputting verilog that's no longer compatible with the latest version of verilator | 18:32 |
| lkcl | arse | 18:33 |
| lkcl | wait... err... no this is nmigen! | 18:44 |
| lkcl | Chips4Makers, found the problem - just as stb was not being asserted for long enough, neither was wen | 23:31 |
| lkcl | just checking now: cocotb-verilator (pre-coriolis2) is now "not freezing ridiculously" | 23:32 |
| lkcl | and it works | 23:38 |
| lkcl | hooorah | 23:38 |
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