| omoiti | Thanks for the information. I'll follow https://git.libre-soc.org/?p=dev-env-setup.git;a=summary to set up a dev environment and see what I can figure out with the unit tests | 00:06 |
|---|---|---|
| programmerjake | omoiti a lot of the bugs are assigned to lkcl since he's the default assignee, not specifically because he's said "I'm working on this bug" | 00:10 |
| programmerjake | also, Welcome! | 00:11 |
| omoiti | Thanks for the clarification on that programmerJake | 00:21 |
| lkcl | jn__, programmerjake all the repos have individual unit tests, cascading upwards | 11:46 |
| jn__ | makes sense | 11:46 |
| lkcl | so there are low-level individual module ones, checking their functionality, then up and up and up | 11:47 |
| lkcl | in the case of the ISA tests the exact same units can be used multiple times | 11:47 |
| lkcl | (three to four) | 11:47 |
| jn__ | (the upper ones might be more appropriately called "integration tests" rather than "unit tests", at some point…) | 11:48 |
| lkcl | ... ah those are the ones such as running microwatt binaries | 11:49 |
| lkcl | although you can see i ran out of time to do it "proper" | 11:50 |
| lkcl | https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;h=550339e46a22169fe19510da5d3032202f3f8aec;hb=5dff543fcedd2c5e2bc4458737be79f5fab49b5b#l54 | 11:50 |
| lkcl | HA! i found the error in the dcache TLB that was corrupting PTEs | 17:59 |
| lkcl | just managed to get a first virtual memory "read" which triggers an MMU RADIX walk, and a second read to the same address returns the same value | 18:02 |
| programmerjake | yay! | 18:50 |
| lkcl | programmerjake: ironically, the next lookup (address+8) gives the same results lol | 19:03 |
| lkcl | doh | 19:03 |
| programmerjake | oops... | 19:04 |
| lkcl | but the key thing is, the TLB entry is good | 19:05 |
| lkcl | so i have a "hit way" error somewhere | 19:05 |
| lkcl | ironically there's no such error in "real mode" | 19:05 |
| lkcl | which is a good sign | 19:05 |
| lkcl | it narrows down considerably the areas i need to examine | 19:05 |
| lkcl | it's still ridiculously complex | 19:06 |
| lkcl | paul mackerras is an absolute genius | 19:06 |
| programmerjake | genius: +1 | 19:19 |
| lkcl | HA! just a wishbone "classic" error in the wb_get function | 19:52 |
| henriok | Hey guys! While standing here at the sidelines, I just want to tell you that it’s pretty inspiring to see this project moving forward. | 20:28 |
| henriok | You rock! | 20:28 |
| lkcl | :) | 21:10 |
| lkcl | well, should be estimated 2-3 weeks you can run a basic GNU/Linux source-built distro on an FPGA | 21:10 |
| jn__ | awesome | 21:24 |
| lkcl | jn__, yeah it's a big step up | 21:26 |
| lkcl | performance will suck but i don't care | 21:27 |
| lkcl | i care about performance second to "functional, executing, working" | 21:27 |
| jn__ | with busybox and musl-libc 200 MHz are snappy, so i guess 50 MHz wouldn't be too bad either | 21:28 |
| jn__ | most importantly, don't install bash-completions :) | 21:28 |
| lkcl | ohh it's a lot lower than 50 mhz :) | 21:28 |
| lkcl | the IPC is somewhere well below 0.15 because it's a Finite State Machine | 21:29 |
| lkcl | the absolute bare minimum simplest (and easily readable) execution / issue engine possible | 21:29 |
| lkcl | it's intended as "readable code that doesn't have wtf pipelining so complex you can barely understand what's going on" | 21:29 |
| jn__ | ah right, that'll affect the performance | 21:29 |
| jn__ | makes perfect sense, simplicity is the way to go at that stage | 21:30 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD | 21:31 |
| lkcl | ha, store works as well https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=20738782e90bd3fe47c2bb6f887456872c7a3ad3 | 22:43 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!