| sasi8985 | Hi all, I now want to develop a core in verilog....can i take small subset like 32 instructions from power isa and develop....finally i want run micropython on that core....s this possible? | 06:01 |
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| programmerjake | if all you care about is writing a really small embedded core, using RV32I might be better, since it's really small. | 06:55 |
| programmerjake | OpenPower works best in bigger systems. if you look in appendix G of the OpenPower v3.1 ISA spec, it has a list of instructions, | 06:55 |
| programmerjake | the rows with XXXX are the ones needed by a basic OpenPower cpu -- it looks like the minimal compliant subset is something like 50-100 instructions | 06:55 |
| programmerjake | now that I look at it again, it lists instructions like cdtbcd Convert BCD to declets (for decimal FP), but it is listed in the minimal required subset -- maybe we should raise this issue with OpenPower, lkcl ? | 06:58 |
| programmerjake | sasi8985 if you like, you could look at https://github.com/programmerjake/simple-riscv-cpu which is a RV32I cpu I wrote for teaching purposes in 2 days, it might be useful for you to write something like it | 07:00 |
| sasi8985 | programmerjake: okay..no problem...i wanted to learn the basic processor design flow from rtl to os booting | 07:04 |
| sasi8985 | So,RV32I is good for start | 07:06 |
| programmerjake | well, that one has close to no software, but should be able to run larger C/C++/Rust programs since I implemented every user-mode instruction in RV32I | 07:06 |
| programmerjake | it has a memory-mapped output port, but no input | 07:07 |
| sasi8985 | okay..i will look at it | 07:08 |
| programmerjake | I didn't implement machine mode or CSRs though, so the standard boot assembly won't work | 07:08 |
| programmerjake | it may have bugs, since I didn't test it that much | 07:10 |
| sasi8985 | programmerjake: does ram.ld initialize ram in cpu and loads main.cpp? | 07:10 |
| programmerjake | ram.ld is the linker script, it tells the linker where in memory it should pack the code and data | 07:11 |
| programmerjake | the cpu just has the ram start initialized to the generated binary | 07:11 |
| programmerjake | it loads the binary and sticks it into the generated HDL here: | 07:12 |
| programmerjake | https://github.com/programmerjake/simple-riscv-cpu/blob/9d07efb854b7348b591a6f656a8620869a8e263a/simple_riscv_cpu/cpu.py#L549 | 07:12 |
| sasi8985 | okay. | 07:15 |
| programmerjake | so, it won't work unmodified in an ASIC since they generally don't support having initialized ram, but it will work fine in some FPGAs (Xilinx Spartan works that way) and in simulation | 07:15 |
| programmerjake | I just simulated it | 07:15 |
| programmerjake | it's designed to be simple to write and understand, not to be fast -- it uses no pipelining whatsoever | 07:16 |
| sasi8985 | okay...actually i don't know python, i know verilog...so i wanted to first write rtl(with pipeline) and then worry about os... | 07:20 |
| sasi8985 | in verilog with $readmem $writememcan we load ram with binary of main.cpp? | 07:22 |
| programmerjake | yes | 07:28 |
| programmerjake | the binary is created by software/Makefile | 07:29 |
| sasi8985 | so, if binary is loaded then i can run programs on rtl...write? | 07:32 |
| programmerjake | you can make it spit out verilog (idk how readable though) by running: | 07:33 |
| programmerjake | (cd software; make) | 07:33 |
| programmerjake | python3 simple_riscv_cpu/cpu.py generate cpu.v | 07:33 |
| programmerjake | it runs the hello-world program when you simulate the cpu, or immediately after reset | 07:34 |
| sasi8985 | okay will try this....thankyou programmerjake :) | 07:35 |
| programmerjake | you will need clang-11 to build software/* | 07:36 |
| programmerjake | you don't need to install a risc-v specific toolchain, any old clang-11 will do | 07:36 |
| programmerjake | (as long as the risc-v backend was compiled in, it usually is) | 07:37 |
| programmerjake | you can get the version I used from: https://apt.llvm.org/ | 07:38 |
| sasi8985 | okay.. | 07:38 |
| *** xws is now known as wxie | 16:06 | |
| lkcl | taking a look at the Compliancy Sections of v3.0C - which are really hard to interpret - "Decimal floating-point (DFP)" is part of the optional linux subset | 18:31 |
| lkcl | which we are *not* implementing - we are implementing the *SFFS* subset... oh and then adding an MMU. | 18:31 |
| lkcl | Scalar binary floating-point (FP) is again optional for the SFFS subset | 18:31 |
| lkcl | but err yeah i'm not seeing anything that says BCD is optional, anywhere | 18:31 |
| lkcl | interesting | 18:31 |
| lkcl | there's only 3 - cdtbcd, addg6s, cbcdtd | 18:31 |
| lkcl | ha! https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/ | 18:31 |
| programmerjake | yeah, my point is it should have been in the decimal fp subset and instead it's in the base isa | 18:32 |
| lkcl | yehyeh | 18:32 |
| lkcl | well apparently the BCD instructions are used for accelerating printf and other things showing decimal numbers as ASCII | 18:33 |
| programmerjake | maybe we can talk them into splitting out another extension: integer decimal | 18:33 |
| lkcl | so i can kiinda understand the justification for having them | 18:33 |
| lkcl | if it was more than 3 instructions (say 15 or greater) i'd say yes to that | 18:34 |
| lkcl | but only 3? mmm... :) | 18:34 |
| programmerjake | well, the add6g maybe, the other two are only used for decoding/encoding the base 1000 encoding used by decimal fp, I don't think they're useful for much else | 18:35 |
| *** xws is now known as wxie | 18:35 | |
| programmerjake | addg6s doesn't have any search results in glibc | 18:38 |
| programmerjake | neither do the other two | 18:39 |
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