| ghostmansd-pc | lkcl: I'm struggling with csv format; let's consider two entries from decode1.vhdl and minor_31.csv | 06:48 |
|---|---|---|
| ghostmansd-pc | (ALU, NONE, OP_AND, NONE, RB, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), -- andc | 06:48 |
| ghostmansd-pc | 0b0000111100,LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,andc,X, | 06:48 |
| ghostmansd-pc | unit fac internal in1 in2 in3 out CR CR inv inv cry cry ldst BR sgn upd rsrv 32b sgn rc lk sgl rpt | 06:49 |
| ghostmansd-pc | the registers follow like this: [in1, in2, in3, out] for vhdl | 06:50 |
| ghostmansd-pc | am I right that csv keeps these in order [in3, in2, in1, out]? | 06:52 |
| ghostmansd-pc | the legend tells it differently: opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS | 07:05 |
| ghostmansd-pc | so, we have [NONE,RB,RS,RA], vs [RS,RB,NONE,RA] for andc, but in1 in vhdl != in1 in csv | 07:10 |
| ghostmansd-pc | also I tried $(python3 src/openpower/decoder/test/test_power_decoder.py), but even without my changes it fails (all 6 tests) | 07:25 |
| ghostmansd-pc | Hm. For things like OP_ADD, the order is actually the same. | 07:56 |
| ghostmansd-pc | I _think_ I added addg6s to csv, but I'm not sure whether it's correct, given the confusion above. | 07:58 |
| ghostmansd-pc | That's how I _suppose_ it should look: 0b0001001010,ALU,OP_ADDG6S,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addg6s,XO, | 07:58 |
| ghostmansd-pc | FWIW, I cannot push even to branch in openpower-isa, it has read-only permissions. | 08:07 |
| programmerjake | lkcl, I just now noticed all the stuff in several days ago about pia and issues with maturin, I lost the notifications on my phone... | 08:21 |
| programmerjake | I'll work on fixing it tomorrow | 08:28 |
| programmerjake | lkcl said: | 08:41 |
| programmerjake | > this is a lesson for you that the current (fast, completely unstable) development pace of rust will not teach you, because they themselves haven't learned it | 08:41 |
| programmerjake | that's not an issue with rust itself (which does have good stable releases), but an issue with how maturin (a totally separate project) recommended specifying the dependency on maturin, they have since changed their recommendation to actually include a version number. | 08:41 |
| programmerjake | basically, what happened is 8 mo ago, when I last worked on pia, pia didn't specify which version of maturin it needs, and since then maturin started to use the new manylinux package naming scheme (pep 600) by default, that new package naming scheme is only supported in versions of pip newer than included in debian 10. pip has supported that since pip 20.3, released Q4 2020. | 09:07 |
| programmerjake | https://github.com/pypa/manylinux/issues/542 | 09:09 |
| programmerjake | maturin's reasoning for switching the default: https://github.com/PyO3/maturin/pull/525#discussion_r627493922 | 09:11 |
| lkcl | toshywoshy: openpowerbot's gone walkies again :) | 14:38 |
| lkcl | it's on OFTC though | 14:38 |
| lkcl | dropped from #microwatt as well | 14:38 |
| ghostmansd | lkcl: Hello Luke! Could you, please, take a look if I have write permissions on openpower-isa? | 15:15 |
| ghostmansd | I made some small commits today, but they're not in repository yet, since I cannot push even to branch. | 15:15 |
| ghostmansd | Also, could you check, please, backlog regarding csv:hdl map and test_power_decoder.py, when you have time? | 15:17 |
| lkcl | ghostmansd: hmmm, since doing the upgrade/downgrade of gitolite3 it's all gone pearshaped. again. | 15:51 |
| ghostmansd | Is it related to an upgrade? I recall I had only libreriscv write permissions... | 15:52 |
| lkcl | ghostmansd: i haven't made *any* changes to the gitolite3 config, since yesterday. | 15:52 |
| lkcl | what error are you getting? | 15:53 |
| lkcl | both www-data and gitolite3 both need write permissions to the repo, that's part of the issue | 15:53 |
| lkcl | can you please try "git push" again | 15:54 |
| ghostmansd | I have only R near openpower-isa repo. Let me re-check though, and I'll post the error. | 15:54 |
| lkcl | errr | 15:54 |
| lkcl | i haven't changed anything so that's a wtf | 15:55 |
| lkcl | oh hang on, somehow the underscore is back | 15:55 |
| lkcl | ok try again | 15:56 |
| lkcl | programmerjake: thanks for taking care of that. it's part of the responsibility, if you are going to use rust, that there exist stable reproducible builds. | 16:18 |
| lkcl | when you recommended "pip install pip" it is now in the archives - forever - we now have to watch out for people in the future trying to do exactly that | 16:19 |
| ghostmansd-pc | lkcl: I checked $(ssh gitolite3@git.libre-soc.org), it's fine now, openpower-isa has RW now. | 16:31 |
| ghostmansd-pc | Before I push, is there some simple check to ensure I haven't broken anything? For now, I've changed power_enums.py and minor_31.csv. | 16:33 |
| lkcl | simple.. mmm.... :) | 16:33 |
| lkcl | run some of the tests. | 16:34 |
| ghostmansd-pc | Ah, BTW, I still desperately need your help on csv vs hdl, at least on ANDC example. :-) | 16:34 |
| lkcl | decoder/isa/test_caller_fp.py | 16:34 |
| lkcl | decoder/isa/test_caller_svp64.py | 16:34 |
| ghostmansd-pc | And also I didn't manage to successfully run test_power_decoder.py. | 16:35 |
| lkcl | normally i would suggest running the HDL co-simulation ones, these run eeeeverything (takes about 1/2 an hour) | 16:35 |
| lkcl | 1 sec | 16:35 |
| ghostmansd-pc | Even on vanilla master. | 16:35 |
| lkcl | ah if that produces an error then don't for goodness sake commit | 16:35 |
| ghostmansd-pc | Perhaps I've been doing it wrong? $(python3 src/openpower/decoder/test/test_power_decoder.py) | 16:36 |
| lkcl | it means.. 1 sec | 16:36 |
| lkcl | no just run that one straight | 16:36 |
| lkcl | yep that's correct | 16:36 |
| lkcl | what happened? | 16:36 |
| ghostmansd-pc | Don't I need to re-build something? | 16:36 |
| lkcl | can you do a "git diff" and upload it to pastebin? | 16:37 |
| lkcl | then i can check it | 16:37 |
| ghostmansd-pc | I can, but it fails even on master. | 16:38 |
| ghostmansd-pc | pastebin: You have exceeded the maximum paste size of 512 kilobytes per paste. PRO users don't have this limit! | 16:38 |
| lkcl | errr what did you do? that's completely excessive, it means you committed something that definitely should not have been committed | 16:39 |
| lkcl | likely a binary file, or an output log file, or something | 16:39 |
| lkcl | email it to me i'll take a look that way | 16:39 |
| lkcl | one change to power_enums.py and one change to minor_31.csv should be about a 512 *BYTES* paste. | 16:40 |
| lkcl | under no circumstances should it be 512k k | 16:40 |
| lkcl | let me know when you've sent it, i can refresh email | 16:41 |
| ghostmansd-pc | I've tried to send the log file :-) | 16:42 |
| ghostmansd-pc | let me simply put stderr output | 16:42 |
| lkcl | i don't need the log file, i need the "git diff" | 16:42 |
| lkcl | i need to know what you've edited so that i can take a look | 16:43 |
| ghostmansd-pc | https://pastebin.com/BZcB9kPd | 16:43 |
| lkcl | if you send me the log file on some "unknown" changes, i have no idea what they are | 16:43 |
| lkcl | yep, i need the *changes* you've made, not the results *of* those changes | 16:44 |
| lkcl | otherwise, i have to guess what changes you made | 16:44 |
| ghostmansd-pc | https://pastebin.com/frEemZrS | 16:44 |
| lkcl | ok brilliant | 16:44 |
| ghostmansd-pc | but again, this is reproducible even on master | 16:44 |
| ghostmansd-pc | so I guess my changes don't matter | 16:45 |
| lkcl | ok give me a sec to run it here | 16:45 |
| lkcl | ah. right. that unit test. | 16:45 |
| lkcl | no, it's massively out of date | 16:45 |
| lkcl | those changes look perfectly reasonable to me, let me check they don't do "damage" by running the HDL test_issuer_svp64.py | 16:47 |
| lkcl | these are git am-apply format, aren't they? | 16:48 |
| lkcl | nggggh :) | 16:50 |
| ghostmansd-pc | nope | 16:50 |
| ghostmansd-pc | I quickly did $(git diff origin/master..HEAD) | 16:50 |
| ghostmansd-pc | but I can send $(git format-patch origin/master) | 16:51 |
| lkcl | you committed some of these... ok, the order's a little awkward for... no that's ok | 16:51 |
| lkcl | i'll add them by hand | 16:51 |
| lkcl | excellent, got them all | 16:52 |
| * lkcl running test_issuer_svp64.py | 16:53 | |
| lkcl | ok that's great, go ahead and git push | 16:54 |
| lkcl | at this low level, even the simulator ISACaller, if any of the simulator tests fail it's indicative of a problem | 16:54 |
| lkcl | we did add some new column formats last year, had to really seriously plan it out, actually write a program which added in the columns and *rewrote* (overwrote) the CSV files with new versions | 16:55 |
| ghostmansd-pc | should I launch test as $(python3 test_issuer_svp64.py), when I do more changes? | 16:56 |
| lkcl | if you have the soc repo checked out, yes. | 16:56 |
| lkcl | the more unit tests you can run the better, but with some of them being very long you have to use pragmatic common sense | 16:57 |
| ghostmansd-pc | I also have a question regarding hdl/csv discrepancy. When I took a look at those, I selected andc instruction, and it seems it uses different "inX" arguments. | 16:58 |
| ghostmansd-pc | (ALU, NONE, OP_AND, NONE, RB, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', NONE), -- andc | 16:58 |
| ghostmansd-pc | LOGICAL,OP_AND,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,andc,X, | 16:58 |
| lkcl | yes. | 16:58 |
| lkcl | ok | 16:58 |
| lkcl | so, a bit of background | 16:58 |
| lkcl | the original POWER1 was an internal *microcode-RISC* architecture | 16:59 |
| lkcl | you can see that clearly from OP_ADD, it's just one (RISC) OP_ADD with 20+ instructions changing carry-in, carry-out, invert-result and invert-input-RA | 16:59 |
| lkcl | very cool, neat idea | 17:00 |
| lkcl | so, when it came to doing LD-ST they wanted to do a ton of modes that you don't normally see in other RISC architectures | 17:00 |
| lkcl | shift-and-mask in particular | 17:00 |
| lkcl | however | 17:00 |
| lkcl | in terms of the number of gates, Shift is *really* expensive, as big as a Multiply, like 12,000 gates or something mad | 17:01 |
| lkcl | this was far too many to put into something as "simple" as a LD/ST | 17:01 |
| lkcl | so what did they do? | 17:01 |
| lkcl | they only put in **ONE** Shift-and-mask engine... | 17:01 |
| lkcl | ... and allowed the LD/ST instruction to pass *PARTIAL* results to the Shift-and-Mask pipeline | 17:02 |
| lkcl | how did they do that? | 17:02 |
| lkcl | they did it by treating RA RB RC RT and RS internally as *broadcast* buses | 17:02 |
| lkcl | such that the LD unit could grab the raw data from the memory bus and then send it on over the "RS" bus to the Shift-and-Mask pipeline, using what's termed "Operand Forwarding" | 17:03 |
| lkcl | and that's why the operands are all over the shop | 17:03 |
| lkcl | some are RS in the 3rd column, where the 1st column is empty | 17:04 |
| lkcl | etc. etc. etc. | 17:04 |
| lkcl | Microwatt decided to respect this design choice | 17:04 |
| lkcl | HOWEVER | 17:04 |
| lkcl | Libre-SOC is designed differently. | 17:04 |
| lkcl | so i moved the operands into "sane" positions. | 17:04 |
| lkcl | so where decode1.vhdl says NONE,RB,RS | 17:05 |
| lkcl | i went, "i am NOT adding a 3rd register to the Logical Pipeline then running it empty 100% of the time!" | 17:05 |
| lkcl | and simply moved RS to position 1. | 17:05 |
| lkcl | RS,RB,NONE | 17:06 |
| richardwilbur[m] | Interesting story behind a fundamental difference in the implementation! | 17:08 |
| lkcl | richardwilbur[m], yeh. microwatt has one single Scalar pipeline, we have 10. | 17:08 |
| lkcl | all separate | 17:08 |
| lkcl | so in Microwatt they *have* to have 3-in 2-out for the ennntirrree (one) pipeline | 17:09 |
| richardwilbur[m] | Even in our first Si? | 17:09 |
| lkcl | whereas i split out Logical pipeline to a separate module | 17:09 |
| lkcl | yes, of course | 17:09 |
| lkcl | and it turns out that, actually, all Logical operations only actually have 2-in (not 3-in) 64-bit regs, and only 1-out (not 2-out) 64-bit regs | 17:10 |
| lkcl | so... errr... remind me why we would add extra wires that would never get used? | 17:10 |
| lkcl | and why would we have them numbered 2 and 3 when 1 is never used? | 17:11 |
| richardwilbur[m] | Sweet! So our first iteration is superscalar, it sounds like. | 17:11 |
| lkcl | it's quite sane logic | 17:11 |
| lkcl | no, not at all. | 17:11 |
| lkcl | it's a FSM. IPC of well below 0.2 | 17:11 |
| richardwilbur[m] | Is that a limitation of the decoder/dispatch or the retirement? | 17:13 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD | 17:14 |
| lkcl | see code comment at top | 17:14 |
| richardwilbur[m] | Wow, so we are going to first Si with the first simple single-issue dispatcher? | 17:17 |
| lkcl | yes. otherwise it would have been necessary to write something far more complex within a very short amount of time | 17:18 |
| lkcl | and we didn't need the hassle | 17:18 |
| lkcl | nor a need for high performance | 17:18 |
| lkcl | it was more important to get *something* functional than it was to get something functional *and* highly optimised | 17:19 |
| ghostmansd | Wow, thank you for an interesting explanation! | 17:20 |
| lkcl | ghostmansd: :) | 17:20 |
| lkcl | POWER1 is like... 1994 | 17:20 |
| ghostmansd | Well, it's quite confusing when you don't have this background :-) | 17:20 |
| richardwilbur[m] | Yes, I understand. Did the vector unit make it into first Si over just 32-bit instructions? (That would still offer a considerable “turbo” mode.) | 17:21 |
| lkcl | it was in the original research paper | 17:21 |
| lkcl | richardwilbur[m]: no, no SVP64. | 17:21 |
| lkcl | it would have taken us quite a way over the gate count | 17:21 |
| lkcl | plus, the development of SVP64 in HDL was *after* the feature freeze decision for the ASIC | 17:22 |
| lkcl | ghostmansd: saw the commits, looks great. comments are good too. am just re-running the unit tests. | 17:22 |
| ghostmansd | When legend tells you one, the table tells you other, and the most obvious test you found doesn't work, it's somewhat confusing. It's a nice story, and I think it deserves to be put somewhere besides this chat. | 17:22 |
| lkcl | i'll run the "big" one, here | 17:22 |
| richardwilbur[m] | Okay. I had a misconception of how much you folks packed into the first Si before I started working on it. | 17:23 |
| lkcl | i had to carry on developing SVP64 so that's why i added the compile-time option in issuer_verilog.py to take it out | 17:24 |
| lkcl | ghostmansd: the "big" one to run is this: python3 simple/test/test_issuer.py nosvp64 | 17:24 |
| richardwilbur[m] | Ah, great idea! | 17:24 |
| lkcl | that takes 20-25 mins here or so | 17:24 |
| lkcl | "nosvp64" takes out all the Draft Vector ISA stuff from the HDL | 17:24 |
| lkcl | off out for a walk, with that running | 17:26 |
| richardwilbur[m] | Enjoy some fresh air and sunshine! | 17:27 |
| richardwilbur[m] | It was very smoky in Montana when we left. We are enjoying clear air in western Washington right now. | 17:29 |
| lkcl | richardwilbur[m], nice :) | 18:04 |
| lkcl | ghostmansd: no errors. all good | 18:04 |
| ghostmansd | Good, I'll continue working on this tomorrow. Should I issue $(simple/test/test_issuer.py nosvp64), or there are more tests that should better be checked? | 18:18 |
| lkcl | ok so test_issuer.py takes so long to run that i tend to only run it just the once before doing a git push. | 18:19 |
| lkcl | if i have several *small* commits (which is preferred: one purpose, one commit), i run much shorter tests | 18:20 |
| lkcl | then *only* just before git push do the large (long) one. | 18:20 |
| lkcl | you just have to use good sense | 18:20 |
| lkcl | if however you are adding something that is not being used by anything else (no dependencies), such as an entirely new unit test, or an entirely new module that doesn't even get used anywhere at all | 18:21 |
| lkcl | then it makes no sense whatsoever to waste an hour running tests. | 18:21 |
| lkcl | ghostmansd: i fixed test_power_decoder.py btw | 18:27 |
| lkcl | the bigendian flag was set inverted | 18:27 |
| richardwilbur[m] | That seems like a pretty big deal. Good find! | 18:28 |
| lkcl | it's a very early unit test, that's redundant effectively, because decoding is used for everything. | 18:29 |
| lkcl | meeting programmerjake richardwilbur[m] klys lxo | 23:14 |
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