| rtharston | Hello libre-soc! I found out about the project yesterday and have been reading about it. I am really intrigued by the goals and what you have achieved so far! | 05:23 |
|---|---|---|
| rtharston | I don't know how much time I'd be able to dedicate to helping right now due to my full-time job and another project I am trying to wrap up, but I would like to help out in some way. | 05:24 |
| rtharston | I haven't done any work in digital logic or HDL yet, but my digital logic class in school was probably my favorite and I've always wanted to do more. | 05:26 |
| rtharston | The top item on my list of projects I want to do is design a CPU and a some supporting chips to make a single board computer of my own, mostly so I can learn all the components. Working with firmware code the last two years at works as helped me learn a lot more about the low level aspects of computers, but I am excited to learn even more, and I think that helping work on this project would be a great way to help the world while I learn | 05:28 |
| rtharston | more about the areas I have always wanted to learn. | 05:28 |
| rtharston | I tried to sign up for the mailing list but haven't seen a confirmation e-mail yet, so I decided to jump on here and give IRC a whirl for the first time (the mailing list is the first of those I have signed up for too actually). | 05:30 |
| rtharston | I won't bore you all with too much more about me for now. I look forward to meeting you all! | 05:31 |
| rtharston | I'm starting to get this IRC thing figured out. I also just found where the chat log is on libre-soc's website, so now I'm not as worried that all my previous messages disappeared when I closed my client. :D While reading through the HDL workflow page I also saw something about checking the spam folder in Gmail so I did that and wouldn't you know, that is where my mailing list confirmation email was, so I'm responded to that now. | 06:23 |
| rtharston | I don't work Sunday so I'll be back Monday to keep reading through the site and perhaps I'll have enough time to take a look at some of the code and learn more about this fascinating nmigen tool. I never thought that using Python to write scripts at work could be useful when designing an SoC! | 06:25 |
| rtharston | Thanks for all the great resources, and ttyl! | 06:25 |
| lkcl | rthartson: great to hear from you | 11:20 |
| lkcl | yes, looking in spam folder is pretty normal these days | 11:21 |
| lkcl | you should see this in the irclogs | 11:21 |
| lkcl | the most extreme use of python in the project involves this | 11:23 |
| lkcl | https://libre-soc.org/3d_gpu/architecture/dynamic_simd/ | 11:23 |
| lkcl | which, alongside the pipeline API, involves | 11:23 |
| lkcl | * overriding arithmetic operators __add__ __gt__ __xor__ etc to provide dynamic partitioned SIMD | 11:24 |
| lkcl | * overriding nmigen's low-level behaviour (TODO) so that "with m.If(x > y)" does the right thing | 11:25 |
| lkcl | * runtime dynamic creation of multiply-inherited objects by providing a Base Class mix-in from a *compile-time* specified base class | 11:26 |
| lkcl | that latter is so that we can pass in a different pipeline "type" - at compile-time - one that is Dynamic-SIMD-aware instead of one that is, well... not | 11:26 |
| kylel | Writing tests, am curious what is supposed to happen when a 32bit is signed extended | 17:23 |
| kylel | into a 64bit | 17:24 |
| kylel | looking at extswsli | 17:24 |
| lkcl | kylel, basically it means "take bit 31 and shove it across bits 32-63" | 17:39 |
| lkcl | but | 17:39 |
| lkcl | butbutbut | 17:39 |
| lkcl | for some reason known only to IBM, they chose to use *MSB0* numbering. | 17:40 |
| lkcl | this creates merry hell and havoc for pretty much anyone and everyone for a period of several weeks to *months*, as your brain is literally re-wired to comprehend arse-backwards numbering | 17:40 |
| lkcl | so when i said, "take bit 31 and shove it across bits 32-63" that's NORMAL industry-standard >>>**LSB0**<<< numberin | 17:41 |
| lkcl | in the Power ISA specifications, you will instead see this: | 17:41 |
| kylel | ok, got the result back from the simulator and it was 0xffffffff...... | 17:42 |
| lkcl | "take bit 63-31 (i.e. bit numbered 32) and shove it across bits (63-32) through to (63-63) aka bits numbered 31 to 0 | 17:42 |
| kylel | threw me for a loop | 17:42 |
| kylel | so I working as designed lol | 17:42 |
| lkcl | yeah, if the 32-bit number was "negative" then the top 4 bytes all contain 1s | 17:43 |
| kylel | Yep, it was. | 17:43 |
| lkcl | you literally have to unscrew the top of your head, take your brain out, turn it round 180 degrees and put it back in, in order to understand Power ISA spec numbering | 17:43 |
| kylel | gotta love big blue | 17:47 |
| kylel | Looked around, is it possible to retrieve the carry registers from sim? | 18:36 |
| Las[m] | When trying to follow https://libre-soc.org/HDL_workflow/coriolis2/, I get `[ERROR] CoreToChip.buildChip(): Pad "p_sys_pllclk" refer net "sys_pllclk" which do not exist in core "ls180".` | 18:48 |
| Las[m] | Does anyone know what this means? | 18:48 |
| programmerjake | rtharston: welcome! | 19:12 |
| lkcl | kylel, yes, sim.CR. | 19:17 |
| lkcl | see... errr... | 19:17 |
| * lkcl goes to find an example | 19:17 | |
| lkcl | sim.crl to access the CRs by "field" (0-7) | 19:19 |
| lkcl | bear in mind these are, once again, in MSB0 number order i.e. *inverted* even from the underlying 32-bit CR they are in! | 19:19 |
| lkcl | and sim.cr is the *actual* 32-bit CR | 19:20 |
| lkcl | there's a class called SelectableInt which takes care of the mind-bending MSB0 order | 19:20 |
| programmerjake | lkcl: I'm planning on working on adding the additional CSV columns to budget-sync tomorrow, i'll be busy today, my housemate's grandparents are visiting | 19:20 |
| lkcl | and *another* class called FieldSelectableInt, where you can pass a SelectableInt to it *and* a list of bit-field mappings, and you can access the FieldSelectableInt as if it was a separate object, but actually maps (for you) onto the underlying SelectableInt | 19:21 |
| lkcl | programmerjake, awesome. nice | 19:21 |
| lkcl | both are in MSB0 order so bear that in mind. | 19:22 |
| lkcl | frequently you will see something "x.value" | 19:22 |
| lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller.py;hb=HEAD#l230 | 19:22 |
| kylel | thank you, yeah been using selectableint | 19:22 |
| lkcl | yeah it "takes care of" the merciless mind-bending bit-order for you :) | 19:23 |
| lkcl | we did it because we had to: it meshes with the specification basically | 19:24 |
| lkcl | Las[m]: drat. that'll take me some time to investigate. | 19:24 |
| Las[m] | lkcl: So the code is broken? | 19:24 |
| Las[m] | If it is broken then it isn't very important I assume, since experiments9 itself won't be very valuable then | 19:25 |
| lkcl | no - it just means, "it'll take some time to investigate" | 19:25 |
| lkcl | in the meantime try this branch: LS180_RC7_FINAL | 19:25 |
| Las[m] | Thanks, of soclayout? | 19:25 |
| lkcl | yes. | 19:25 |
| lkcl | also, bear in mind, we had to use a specific tag of yosys. it's in the build script. | 19:26 |
| Las[m] | Oh yeah. | 19:26 |
| Las[m] | Thanks, I'll try using that version of yosys | 19:27 |
| lkcl | 049e3abf9 | 19:27 |
| lkcl | git checkout ^^ | 19:27 |
| lkcl | if it doesn't "work" we'll need to do an in-depth investigation, triaging exactly what versions of exactly what software you've installed etc. etc. | 19:28 |
| lkcl | and do a full repro investigation | 19:29 |
| lkcl | which, honestly, i will need a bit of a mental run-up to prepare for :) | 19:29 |
| Las[m] | Welp, even with the older Yosys it still fails. | 19:48 |
| Las[m] | I'll try and replicate the exact steps in Debian rather than in Nix | 19:49 |
| Las[m] | programmerjake: Are you still working on Kazan or is that no longer relevant for Libre-SoC/ | 20:56 |
| Las[m] | ? | 20:56 |
| programmerjake | I'm still working on it, but have been distracted with other stuff, the most recent major work was working on a new math library shared between Kazan and Rust's standard library: | 20:57 |
| programmerjake | https://salsa.debian.org/Kazan-team/vector-math | 20:58 |
| programmerjake | https://bugs.libre-soc.org/show_bug.cgi?id=632 | 21:00 |
| Las[m] | Thanks. | 21:00 |
| programmerjake | https://github.com/rust-lang/portable-simd/issues/109 | 21:02 |
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