lkcl | Las[m], you got the cc email discussion with tpearson, right? | 09:08 |
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Las[m] | I did lkcl | 09:09 |
Las[m] | Do you have any idea when this might be shippable? | 09:09 |
lkcl | no i don't. worth emailing and asking | 09:10 |
Las[m] | lkcl: When targeting an ECP5, is the pinmux directory needed at all? | 16:17 |
lkcl | Las[m], no not really | 16:58 |
lkcl | the pinmux is used to define the ASIC pinouts | 16:58 |
lkcl | i didn't bother with that with the ECP5, just hardcoded a minimum subset of peripherals using the standard litex methodology | 16:58 |
lkcl | except... 1 sec... | 16:59 |
lkcl | did i route them via the JTAG boundary-scan? | 16:59 |
lkcl | i can't remember. | 16:59 |
lkcl | kylel, nicely done on ExpectedState. getting there. you saw my bugreport comments? | 17:00 |
lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=686#c48 | 17:01 |
lkcl | the DecoderTestCase.create_regs() would be where "yield from" would be done on sim, passed in to a TestState. | 17:01 |
lkcl | exactly as is done for test_core | 17:01 |
lkcl | but now with ExpectedState intsance and Sim instance | 17:02 |
lkcl | not HDL instance and Sim instance | 17:02 |
lkcl | then you can just call State.compare()! | 17:03 |
lkcl | or the looping-compare function | 17:03 |
lkcl | which, hm, we need to move from test_core.py | 17:03 |
lkcl | 1 sec | 17:03 |
kylel | sounds good, senior moment for me on the compare | 17:05 |
lkcl | :) | 17:05 |
lkcl | i just realised, you only need a 2-line check_regs | 17:05 |
kylel | just pass self as the dut right? | 17:05 |
lkcl | with testdic = {'sim': sim, 'expected': e} | 17:05 |
lkcl | yes | 17:05 |
kylel | yep, cool | 17:05 |
lkcl | 1 sec am just moving teststate_check_regs into state.py | 17:05 |
kylel | no problem | 17:06 |
lkcl | done | 17:06 |
lkcl | kylel, https://bugs.libre-soc.org/show_bug.cgi?id=686#c49 | 17:08 |
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Las[m] | lkcl: I'm asking because when building the verilog using `issuer_verilog.py`, it loads the pinmux files, even if you're targeting the ECP5. | 17:22 |
Las[m] | Do you think I could just remove this code and it would still work then? | 17:22 |
Las[m] | I suppose I can check if it builds and if the outputs are different | 17:22 |
lkcl | i.. ah... it sounds so simple when asked that way | 17:23 |
lkcl | however the consequences - the amount of work involved - is quite considerable | 17:23 |
lkcl | given that - not joking - it was about probably... TWELVE WEEKS of work to link the pinmux in to the litex code | 17:24 |
lkcl | it ties directly into the JTAG boundary scan | 17:24 |
lkcl | which required the creation of *PAIRS* of Signals | 17:25 |
lkcl | (which, no way in hell was i going to manually create those, hence why pinmux auto-generates them) | 17:25 |
lkcl | bear in mind, like i said earlier, each signal can be up to **THREE** actual Signals | 17:25 |
lkcl | In | 17:25 |
lkcl | Out | 17:25 |
lkcl | Direction-Enable | 17:25 |
lkcl | it was a mad amount of work | 17:26 |
lkcl | even explaining it is itself complex | 17:26 |
lkcl | and guiding you through it to step *BACKWARDS* - by *UNDOING* necessary work | 17:26 |
lkcl | is not really something i'd be happy to spend time on | 17:26 |
lkcl | by contrast | 17:26 |
lkcl | if you said, "i'd like to help with the next ASIC to create a pinmux for that, as a way to understand the first ls180 one" | 17:27 |
lkcl | i'd be more than happy to do that | 17:27 |
kylel | lkcl: in the caller test check_regs, I won't be able to use yield from correct? | 18:38 |
Las[m] | lkcl: Thanks for the answer. Kind of related: I assume you use the latest commit of Litex on git.libre-soc.org, but what about the other compoments like litedram? How do you get the correct commit? | 18:47 |
lkcl | no, i haven't used the latest version of litex. i use the tagged version | 19:36 |
lkcl | https://git.libre-soc.org/?p=litex.git;a=commit;h=35929c0f8a8f1cc098a6b6ebb569caca8df8c08d | 19:36 |
lkcl | tag "24jan2021_ls180" | 19:36 |
lkcl | litex's own initialisation scripts *should* pull in specific submodules for that | 19:37 |
lkcl | kylel, hmm good question. 1 sec let me check | 19:37 |
lkcl | for default args, no spaces are used btw | 19:38 |
lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=950ec659d34059398f19f4fb61524265fbba7bff | 19:38 |
lkcl | cr=0, pc=0, not cr = 0, pc = 0 | 19:38 |
lkcl | just a convention | 19:38 |
lkcl | but we stick to PEP8, so... | 19:39 |
lkcl | where are we... | 19:39 |
lkcl | run_tst_program... | 19:40 |
lkcl | run_tst... | 19:40 |
lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_runner.py;hb=HEAD | 19:41 |
lkcl | return simulator at the bottom of run_tst()... | 19:42 |
lkcl | line 152.. https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_runner.py;hb=HEAD#l152 | 19:42 |
lkcl | yes that can and should use yield from. | 19:42 |
lkcl | the nmigen simulator instance *requires* using "yield from" | 19:43 |
lkcl | you'll be passing that in to teststate_check_regs() | 19:43 |
lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;h=57f77fcff41936944eddccf7f008d6dc10c82afe;hb=HEAD#l169 | 19:43 |
lkcl | so you still have to call "yield from teststate_check_regs()" | 19:44 |
lkcl | and that in turn makes anything that *uses* that function *also* a generator... | 19:44 |
lkcl | and therefore, if that function is also called check_regs() | 19:45 |
lkcl | then yes, you must call "yield from" | 19:45 |
lkcl | basically anything that uses a generator is also a generator | 19:45 |
lkcl | does not matter *in any way* how deep the function call stack goes. | 19:45 |
Las[m] | lkcl: Litex doesn't use submodules seemingly, and it seems that the `litex_setup.py` script explicitly pulls the latest version of the script master, even if you're trying to use an old commit! | 19:51 |
kylel | lkcl, yeah which I'm circling back to yesterday, a yield from there and the unit test doesn't execute | 20:04 |
programmerjake | lkcl, new bcd test that works w/o pia: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_bcd_full.py;h=719c32be636339fc3378829c9c0e0cc918971361;hb=refs/heads/xlen | 22:09 |
lkcl | programmerjake, excellent | 22:43 |
lkcl | ahh you know we have the compiler which (redundantly) creates dpd_to_bcd and bcd_to_dpd? | 22:44 |
lkcl | it passes? (if so that's good enough, let's close the bugreport and get you some $) | 22:45 |
lkcl | kylel, do commit it like last time, let's have a look | 22:46 |
* lkcl programmerjake running it now to check | 22:47 | |
programmerjake | well...if we used the exact same dpd_to_bcd and bcd_to_dpd, it's not much of a test...hence why I used the version converted from pia | 23:01 |
programmerjake | it passed the test when I tried | 23:01 |
kylel | lkcl,https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=e70634a08b51f7400621a1a39c610bb171eea244 | 23:09 |
kylel | btw, python didn't like the one liner if else changes you made | 23:09 |
kylel | in state | 23:10 |
lkcl | kylel, doh | 23:33 |
lkcl | programmerjake, excellent | 23:33 |
lkcl | confirmed operational here, too | 23:33 |
lkcl | kylel, you can't run "yield" on something that isn't a generator | 23:33 |
lkcl | you can only run "yield" from functions that are generators. | 23:34 |
lkcl | is simstate.compare() a generator? | 23:34 |
lkcl | hmmm... something very odd going on | 23:39 |
lkcl | i know what it is. the results have to be obtained within run_tst's "process()" function. | 23:41 |
lkcl | drat | 23:41 |
lkcl | because it's the "process()" function in which "yielding" is being run | 23:41 |
lkcl | ok i'll sort that | 23:41 |
kylel | yeah, that's what I meant from the rabbit hole comment...at that point I was like "oh boy" | 23:41 |
lkcl | nggh i'm about 3 levels deep in that already... | 23:45 |
lkcl | have to pass in to_test, dut, and code args... urr | 23:45 |
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