Thursday, 2021-09-16

lkclLas[m], you got the cc email discussion with tpearson, right?09:08
Las[m]I did lkcl09:09
Las[m]Do you have any idea when this might be shippable?09:09
lkclno i don't. worth emailing and asking09:10
Las[m]lkcl: When targeting an ECP5, is the pinmux directory needed at all?16:17
lkclLas[m], no not really16:58
lkclthe pinmux is used to define the ASIC pinouts16:58
lkcli didn't bother with that with the ECP5, just hardcoded a minimum subset of peripherals using the standard litex methodology16:58
lkclexcept... 1 sec...16:59
lkcldid i route them via the JTAG boundary-scan?16:59
lkcli can't remember.16:59
lkclkylel, nicely done on ExpectedState. getting there. you saw my bugreport comments?17:00
lkclhttps://bugs.libre-soc.org/show_bug.cgi?id=686#c4817:01
lkclthe DecoderTestCase.create_regs() would be where "yield from" would be done on sim, passed in to a TestState.17:01
lkclexactly as is done for test_core17:01
lkclbut now with ExpectedState intsance and Sim instance17:02
lkclnot HDL instance and Sim instance17:02
lkclthen you can just call State.compare()!17:03
lkclor the looping-compare function17:03
lkclwhich, hm, we need to move from test_core.py17:03
lkcl1 sec17:03
kylelsounds good, senior moment for me on the compare17:05
lkcl:)17:05
lkcli just realised, you only need a 2-line check_regs17:05
kyleljust pass self as the dut right?17:05
lkclwith testdic = {'sim': sim, 'expected': e}17:05
lkclyes17:05
kylelyep, cool17:05
lkcl1 sec am just moving teststate_check_regs into state.py17:05
kylelno problem17:06
lkcldone17:06
lkclkylel, https://bugs.libre-soc.org/show_bug.cgi?id=686#c4917:08
*** ibot is now known as Guest52117:12
*** ibot is now known as Guest211817:19
Las[m]lkcl: I'm asking because when building the verilog using `issuer_verilog.py`, it loads the pinmux files, even if you're targeting the ECP5.17:22
Las[m]Do you think I could just remove this code and it would still work then?17:22
Las[m]I suppose I can check if it builds and if the outputs are different17:22
lkcli.. ah... it sounds so simple when asked that way17:23
lkclhowever the consequences - the amount of work involved - is quite considerable17:23
lkclgiven that - not joking - it was about probably... TWELVE WEEKS of work to link the pinmux in to the litex code17:24
lkclit ties directly into the JTAG boundary scan17:24
lkclwhich required the creation of *PAIRS* of Signals17:25
lkcl(which, no way in hell was i going to manually create those, hence why pinmux auto-generates them)17:25
lkclbear in mind, like i said earlier, each signal can be up to **THREE** actual Signals17:25
lkclIn17:25
lkclOut17:25
lkclDirection-Enable17:25
lkclit was a mad amount of work17:26
lkcleven explaining it is itself complex17:26
lkcland guiding you through it to step *BACKWARDS* - by *UNDOING* necessary work17:26
lkclis not really something i'd be happy to spend time on17:26
lkclby contrast17:26
lkclif you said, "i'd like to help with the next ASIC to create a pinmux for that, as a way to understand the first ls180 one"17:27
lkcli'd be more than happy to do that17:27
kylellkcl: in the caller test check_regs, I won't be able to use yield from correct?18:38
Las[m]lkcl: Thanks for the answer. Kind of related: I assume you use the latest commit of Litex on git.libre-soc.org, but what about the other compoments like litedram? How do you get the correct commit?18:47
lkclno, i haven't used the latest version of litex. i use the tagged version19:36
lkclhttps://git.libre-soc.org/?p=litex.git;a=commit;h=35929c0f8a8f1cc098a6b6ebb569caca8df8c08d19:36
lkcltag "24jan2021_ls180"19:36
lkcllitex's own initialisation scripts *should* pull in specific submodules for that19:37
lkclkylel, hmm good question.  1 sec let me check19:37
lkclfor default args, no spaces are used btw19:38
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=950ec659d34059398f19f4fb61524265fbba7bff19:38
lkclcr=0, pc=0, not cr = 0, pc = 019:38
lkcljust a convention19:38
lkclbut we stick to PEP8, so...19:39
lkclwhere are we...19:39
lkclrun_tst_program...19:40
lkclrun_tst...19:40
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_runner.py;hb=HEAD19:41
lkclreturn simulator at the bottom of run_tst()...19:42
lkclline 152.. https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_runner.py;hb=HEAD#l15219:42
lkclyes that can and should use yield from.19:42
lkclthe nmigen simulator instance *requires* using "yield from"19:43
lkclyou'll be passing that in to teststate_check_regs()19:43
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;h=57f77fcff41936944eddccf7f008d6dc10c82afe;hb=HEAD#l16919:43
lkclso you still have to call "yield from teststate_check_regs()"19:44
lkcland that in turn makes anything that *uses* that function *also* a generator...19:44
lkcland therefore, if that function is also called check_regs()19:45
lkclthen yes, you must call "yield from"19:45
lkclbasically anything that uses a generator is also a generator19:45
lkcldoes not matter *in any way* how deep the function call stack goes.19:45
Las[m]lkcl: Litex doesn't use submodules seemingly, and it seems that the `litex_setup.py` script explicitly pulls the latest version of the script master, even if you're trying to use an old commit!19:51
kylellkcl, yeah which I'm circling back to yesterday, a yield from there and the unit test doesn't execute20:04
programmerjakelkcl, new bcd test that works w/o pia: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_bcd_full.py;h=719c32be636339fc3378829c9c0e0cc918971361;hb=refs/heads/xlen22:09
lkclprogrammerjake, excellent22:43
lkclahh you know we have the compiler which (redundantly) creates dpd_to_bcd and bcd_to_dpd?22:44
lkclit passes? (if so that's good enough, let's close the bugreport and get you some $)22:45
lkclkylel, do commit it like last time, let's have a look22:46
* lkcl programmerjake running it now to check22:47
programmerjakewell...if we used the exact same dpd_to_bcd and bcd_to_dpd, it's not much of a test...hence why I used the version converted from pia23:01
programmerjakeit passed the test when I tried23:01
kylellkcl,https://git.libre-soc.org/?p=openpower-isa.git;a=commit;h=e70634a08b51f7400621a1a39c610bb171eea24423:09
kylelbtw, python didn't like the one liner if else changes you made23:09
kylelin state23:10
lkclkylel, doh23:33
lkclprogrammerjake, excellent23:33
lkclconfirmed operational here, too23:33
lkclkylel, you can't run "yield" on something that isn't a generator23:33
lkclyou can only run "yield" from functions that are generators.23:34
lkclis simstate.compare() a generator?23:34
lkclhmmm... something very odd going on23:39
lkcli know what it is. the results have to be obtained within run_tst's "process()" function.23:41
lkcldrat23:41
lkclbecause it's the "process()" function in which "yielding" is being run23:41
lkclok i'll sort that23:41
kylelyeah, that's what I meant from the rabbit hole comment...at that point I was like "oh boy"23:41
lkclnggh i'm about 3 levels deep in that already...23:45
lkclhave to pass in to_test, dut, and code args... urr23:45

Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!