Friday, 2021-09-17

lkclgaah that's a mess but it's functional00:08
lkclkylel, got it "working"00:09
kylelnow there's a vote of confidence I can get behind00:13
kylelthank you for that effort, I had to imagine that was messy00:14
*** kylel1 is now known as kylel02:37
lkclkylel, it was... unexpected, shall we say15:00
lkclanother thing that "emerges" :)15:01 run_tst_program basically should become part of the (planned) base class that all unit tests use15:02
lkclmore to the point15:02
lkclsplit completely out so that test cases are "accumulated" in the exact same way they are for HDL15:03
lkcllike this15:03
lkclevery single one of those *should* have an "ExpectedState"15:04
lkclbut it's ok if they don't: to be meaningful they simply have to be run against 2 "things"15:04
lkclbut the idea is that those test cases which *do* have ExpectedState15:04
lkcllook *EXACTLY* like alu_cases.py15:05
lkcland consequently can compare against *THREE* things15:05
lkcl1) the ISACaller simulator15:05
lkcl2) the HDL15:05
lkcl3) *the ExpectedState()*15:05
lkclso that's our goal15:05
lkclto split out the test cases into a base class and "cases", to look *exactly* like alu_cases.py15:06
lkclan intermediary goal is to add, to one (and only one, for now) of, an ExpectedState()15:07
lkclthen to allow that to "work its way down" to's check_regs()15:07
lkcland that dict testdic would become15:08
lkcl    testdic = {'sim: sim, 'hdl': core, 'expected': expectedresults}15:08
lkcland, ta-daaa, we have a useful API :)15:09
kylelso basically add an optional expected for add_case and then in check_regs choose the proper dict?15:19
lkclyou were off for a while :)16:13
lkcli explained it in the bugreport16:13
lkclit should be straightforward and much easier to do than the non-HDL case16:14
kylelfamous last words :)16:19
kylelI was thinking about expected and TestCase earlier16:20
kylelwould it be too simple or naive to think to just check in TestCase if to_test is expected and basically skip past the creation part leaving it basically as is?  that way it would basically fly through the check_regs in test_core16:22
lkcloh, err... hmmm17:22
lkcllike, be ignored17:22
lkclunless called at the end17:22
lkcloh, i know: have an argument to check_regs which allows it to be skipped17:23
lkclbtw, deep breath: we need to work out how to run arbitrary "things", independently17:23
lkclnow, at the moment, they are run side-by-side17:24
lkcltrying to run multiple simultaneous generators, this will be COMPLETELY mental :)17:24
lkclso one option is to do them *one at a time*17:24
lkcland to *accumulate* results...17:24
lkclthen *AFTERWARDS* run the comparison(s)17:24
lkclotherwise we have to look at doing some sort of multi-threading nightmare17:25
lkclmy feeling is, running the HDL and accumulating "results", then doing the same thing for ISACaller, and the same for qemu, and ... etc. etc.17:59
lkclthis is the "sane" way to do it17:59
programmerjakewell...if the stuff can be run in a different process and results piped or otherwise sent using interprocess communication, python does have all the async/await stuff needed to handle it all in parallel18:03
programmerjakealternatively rely on pytest-xdist to provide test parallelism and just run it all single-threaded/single-process (except calling qemu/gdb/etc.)18:06
programmerjakelkcl, tgx for handling #68518:06
*** acid115 <acid115!~s@> has left #libre-soc18:23
lkclprogrammerjake, indeed it does... worked with it several times - i'm just slightly nervous about jumping straight to that style, as a first pass, if you know what i mean19:21
lkclbtw what do you think about tackling the PartitionedSignal integration to nmigen? there's a *lot* of budget allocated to it19:21
lkclkylel, i'm going to have a go at hacking to separate out HDL-result-generation from Sim-result-generation19:22
lkclit occurs to me that now TestState exists it can be used (manually) to extract state. which is kinda cool.19:23
lkclahh wait... have to do memory-checking first19:23
kylelwhere's that taking place?19:36
kyleln/m just saw your comment19:38

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