Saturday, 2021-11-06

octaviuslkcl, the ls180 pinout (on the wiki and in the spec file) specifies the package having 32 pins on each side, with width 2 (no units). What does the width correspond to?14:05
lkclwidth 2? i don't understand what you mean14:29
lkclBank N (32 pins, width 2)14:29
lkclignore it14:29
octaviusThe spec python file creates tuples like this: ('N', (32, 2))14:30
octaviusDo I still need to include this parameter 2?14:30
lkcl1 sec i need to examine the source code14:30
octaviusI tried to look for the usage of it, but couldn't figure it out14:31
lkclthe entirety of that program is undocumented and quite complex14:31
octaviusAh ok14:31
lkcli suspect it is the number of mux options14:32
lkclwhere because the code fails if it is set to 1 it is set to 2 instead14:32
lkcl    pinbanks = OrderedDict((14:32
lkcl        ('N', (32, 2)),14:32
lkclset to 2.14:32
lkcllook at the i_class file14:32
octaviusin, self.muxwidths[bank] = muxwidth14:33
lkcl    pinbanks = {14:33
lkcl        'A': (28, 4),14:33
lkcl        'B': (18, 4),14:33
lkcl        'C': (24, 1),14:33
lkcl        'D': (93, 1),14:33
lkclok so it probably does cope with a mux value of 114:33
octaviusyeah, so that means bank A has a 4-way mux?14:33
lkclfor such compact code it is quite ridiculously complex data structures14:34
lkclwith a lot of reordering of dicts-of-something-of-something-else14:35
lkclinto lists-of-dicts-of-the-something-else-by-the-first-thing14:35
lkcldict[a][b] -> dict[b][a]14:35
lkclbecause of the mappings from functions to pins14:35
lkclyou also need to know which pins have which functions14:36
lkclstarting out from dict[pins][functions]14:36
lkclyou have to create dict[functions][pins]14:36
lkcl*and* then verify that there is no overlap14:36
lkcl*and* identify missing (unused) pins14:37
lkcl*and* identify missing functions from a specification (called a "scenario")14:37
lkclimagine you are designing an SoC14:37
lkclit has a complex multiplexer14:37
lkclbecause you have 1,000 actual functions but only say 250 pins (to save cost)14:38
lkclif you get *ONE* of those pins wrong, for a particular scenario (one multiplexed function that is needed which the customer can't bring out because it conflicts with another function for the same pin)14:38
lkclyour customer will simply go "well that's useless, i'll buy a competitor's product instead"14:39
lkclhence you actually have to *specify and test* the scenarios14:39
lkclwhich means being able to say what functions you want14:39
lkclthen be able to *remove* them from the available pinset14:39
lkcland, if at the end of removing all pins from "available" you have completed that without any being missing14:40
lkclthen the scenario can be declared a "success"14:40
lkcl(and, it acts as a Reference Design for that customer, for that scenario)14:40
lkclfrickin complicated in other words14:41
octaviusLet's see if I understood what you were talking about. The user of the script specifies the functions (sdram, uart, vdd, etc.) and where they connect to on the package (by instantiating them in the "ps" or PinSpec object). The code then has to create the opposite dictionary (pins to functions) and confirm for any collisions?14:42
octaviusIn this specific case (ngi router), as we are NOT using muxing atm, the problem should be a little bit simpler for the code to test, correct?14:43
lkclcorrect, and correct15:17
lkclah... actually there's a 3rd phase15:17
lkcland that's what doesn't need to be done15:17
lkclbecause, duh, the pinouts are one-to-one, yes.15:18
octavius3-phase is muxing conflicted functions?15:18
lkclchecking multiple scenarios15:18
lkclline 247: an "Industrial" scenario15:19
lkclbtw, this is where memory-maps would be specified:15:21
lkclfor the peripherals to have their CSRs (Control Status Registers) memory-mapped15:21
lkclif not specified, the memory-map locations are auto-generated15:22
octaviusok. So in the i_class line 63 example, jtag and fb peripherals don't have CSRs? Or are they left to be auto-generated15:23
octaviussorry, meant memory-mapped CSRs15:24
lkcljtag is totally separate yes15:24
lkcland FlexBus (motorola) is a general-purpose Memory Bus15:25
lkclcovers AT/XT, MCU 8080, SDRAM, and several more15:25
lkcloctavius, i just updated to python315:33
lkclthere may be some things missing15:33
lkclthe conversion is necessary because jean-paul converted coriolis2 to python3 as well15:34
octaviusMy system has both Python 2 and 3. Should I keep using 2 while getting the router pinout made?15:38
lkclboth work fine15:38
lkcli added the spec, the markdown file generates great15:39
lkclPLL goes into the top leeeeft...15:41
lkclcouple of RGMII interfaces added so you can see how it's done15:51
lkclthey're 18 pins each.  not 20.  close.15:52
octaviusThanks, should be easier now15:52
octaviusI'll add the steps you did to add a new chip class to the bug as well (as I didn't add the import statements after creating ngi_router)15:52
lkclok good idea.15:53
lkclreally should be documented15:53
lkcl5x20-5x18 = err... 5x2=1015:55
lkclthat's 10 spare15:56
lkclbtw you saw how it was +    ps.rgmii("1", ('N', 10), 0, 0, 18)15:56
lkclthe 1st argument "1" is the suffix15:56
lkclso for adding 2 USB/ULPI interfaces it would be ps.ulpi("0"....) and ps.ulpi("1"....)15:57
lkcli don't think the USB3300 is properly ULPI, but UTMI15:57
lkclULPI is DDR (double data rate) and the pincount for data buses is 4 (UTMI is 8)15:58
lkcldatasheets need to go into towards the end15:58
lkclso that they end up in the markdown file15:58
octaviusHow should datasheet URLs be included? as a variable or a print statement?15:59
lkcllike the others16:00
lkclsee for one of the larger ones16:00
lkcl1 sec16:00
octaviusok will do16:00
lkclapparently i have it in the template for the mdwn16:00
lkclgrep the source for "datasheets"16:01
octaviusso what do the "c_" and "m_" prefixes mean ("" and "")? M for module?16:02
lkclIIT Madras Shakti Project prefixes16:03
lkclmobile class16:03
lkclembedded class16:03
lkclindustrial class16:03
octaviusI don't see "e_class"16:03
lkclnot important16:05
lkclhmmm... the USB3300 is 8-way bi-directional16:06
lkclwhereas the TUSB1210 is 4-pin TX DDR, 4-in RX DDR16:06
octaviusyeah, the direction is specified by USB330016:06
lkclwhere the heck have i seen DDR??16:08
lkclit was on the Allwinner A20 i'm sure16:08
lkclTUSB1210 is likewise 8-bit16:08
lkclST's ULPI as well and both write the "# Reference Datasheets", however I don't see how the datasheet string can be adjusted on a per-project basis. Should I just append the new datasheets to
lkclyes go for it16:11
lkcluse the links at https://ftp.libre-soc.org16:12
lkclahh NXP do a DDR ULPI.  ah ha! it _is_ part of the spec16:12
lkclhmm but they are max 1.9v. arse16:13
lkclah ha!16:15
lkclbut no DDR16:16
octaviusI'm a little confused why you mention DDR with the USB phy. Is ULPI compatible with DDR?16:17
lkcltwo last possibilities to explore then screw it16:21
lkclgaah i used to do this kind of fast research all the time16:22
lkclSTULPI01A, hooraaaay16:24
lkcl3.3v (actually 3.6 max) Digital IO16:25
lkcland it's capable of 4-pin bi-directional DDR16:25
lkclout damn time16:25
octaviusAh, Double-Data Rate just means data coming on both edges of the clock, doesn't specifically mean DDR RAM (that's the only association I had)16:28
lkclRAM buses are also double data rate16:28
octaviusYeah, I didn't realise that other buses come in a DDR flavour as well16:29
octaviusalthough it makes sense16:29
lkclthis one
lkclopentapeoutdev conference in... 1.5 hours?16:31
octaviusDo you have the LAN PHY datasheet on ftp?16:32
lkclwhere's the link (youtube)?16:32
lkclLAN PHY? ah no16:32
lkcl1 sec16:32
octaviusLink to the stream day 116:32
octaviusThanks, I couldn't find it on their website:
lkclfinding china-sourced datasheets is a f*****g nuisance16:36
lkclyou often have to go to things like sparkfun or adafruit16:36
octaviusor look at dodgy datasheet sites16:37
lkclfortunately i spent 5+ years doing this so know... yeah16:37
octaviuswhich usb phy did you decide on?16:38
lkclthe RTL8211 doesn't seem to have collision16:39
lkclalthough if we fit 12 pins the USB3300 can be used fine16:39
lkclnice.  TXDLY and RXDLY add 2ns timing delay to clock xmit / rx16:41
octaviusDo we need a delay?16:42
lkclso if you screw up inside your ASIC you can botch-fix it16:42
octaviusAlso, I don't see the difference in USB3300 and STULPI01A ULPI interfaces (same 12 pins).16:44
octaviusCan you use half the data lines or something?16:44
tplatenI'm currently testing MTSPR and MFSPR. Those instructions get issued to the mmu/fsm but issuer.insn_done never goes 116:54
lkcltplaten, look at how the DIV FSM works. the code is unfinished so it is unlikely to be setting ready/valid signalling17:48
octaviusPerhaps a noobie question, but what does the [m] suffix mean after some people's usernames?17:58
jnit usually means someone is joining from Matrix17:58
jn(as in
octaviusthanks, I had a hunch17:59
octaviusbut wasn't sure17:59
tplatenI first thaught about gender17:59
tplatenNo its matrix17:59
tplatenAs there is no [f] or [nb]18:00
jnthe OpenTapeout conference is starting NOW (livestream @
Veera[m]Did anyone used symbiflow-install and got benefit? Asking for personal satisfaction for work!23:32

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