lkcl | Veera[m], that'll be me, as i am the only one with an arty-a7, and i've a huge number of other things to do, sorry :) | 12:04 |
---|---|---|
lkcl | cesar, ha! ReservationStations2 works! | 13:10 |
lkcl | and i got rid of redundant wrmask | 13:10 |
lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=742 | 13:10 |
lkcl | ha! i also managed to reduce the ReservationStations FSM down to 2 cycles per RS | 13:17 |
cesar | Nice! | 13:32 |
lkcl | yeah | 13:32 |
lkcl | i'm currently running through test_issuer using it in "one RS" mode | 13:33 |
lkcl | num_rows=1 | 13:33 |
lkcl | works fine for ALU, Logical, CR - Branch i am doing now | 13:33 |
lkcl | so if it works with one RS, we don't need FunctionUnitBaseSingle | 13:34 |
lkcl | Branch is fine | 13:34 |
lkcl | the DIV FSM however _will_ need FunctionUnitBaseSingle | 13:35 |
lkcl | and any other FSMs | 13:35 |
lkcl | ShiftRot is good | 13:37 |
cesar | Do we actually have some multi-stage pipelined function units? Maybe for floating-point? | 13:37 |
lkcl | yes, i deliberately made mul a 2-stage | 13:37 |
lkcl | err for some reason mul isn't in testissuer! | 13:38 |
cesar | I guess it takes too long... There's a compunit unit test for it, I think. | 13:39 |
lkcl | that's the mul long one | 13:39 |
lkcl | i'm adding it now | 13:40 |
lkcl | trundle, trundle... | 13:40 |
lkcl | urr zzzz 40x random values per test times 10 tests zzzz | 13:42 |
lkcl | done, all good! | 13:43 |
lkcl | ok committed | 13:45 |
* lkcl running a full test just to make sure | 13:46 | |
lkcl | cesar, i made some notes about the RSes, num_rows has to be set to 1 | 15:48 |
lkcl | and, also, i just added some Read-after-Write Hazard vectors | 15:48 |
lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=737#c12 | 15:48 |
lkcl | actually, err, we don't need both RaW and WaR, only need one of those | 15:49 |
lkcl | will sort that | 15:49 |
cesar | Sure. | 16:10 |
* cesar is still getting familiar with the Pipeline API. | 16:11 | |
cesar | No problem there, just need time. | 16:12 |
* lkcl thinking | 16:30 | |
lkcl | 1.5 hrs until the 2nd day opentapeoutdev https://www.youtube.com/watch?v=sunruF6ryso | 16:33 |
lkcl | cesar, some signals, like "Stall" or "Exception happened" still have to be global in nature | 16:34 |
lkcl | and fed from InOrderIssuer by routing out of Stages into other Stages | 16:35 |
lkcl | which is a bit awkward | 16:35 |
cesar | It may be possible to isolate them in specially crafted Pipelines, manipulating ready/valid directly (not using the Pipeline API) | 16:39 |
cesar | (I'm still planning an approach, considering what the Pipeline API has to offer) | 16:52 |
lkcl | cesar, yes, it would | 17:32 |
lkcl | however bear in mind, if we want to re-use the components later, or split down into smaller combinatorial blocks that are auto-chained together (for lower-speed ASICs) | 17:32 |
lkcl | the Stage API can handle that | 17:32 |
lkcl | _without_ massive rewrites | 17:32 |
cesar | Got it. | 17:33 |
lkcl | if done as an FSM-based Stage, it is a hybrid of the two approaches | 17:34 |
lkcl | still ready/valid is directly exposed | 17:34 |
lkcl | but then managed by a chain of ControlBase derivatives | 17:34 |
lkcl | programmerjake, i corrected the DIV FSM, FSMDivCoreStage to properly conform to the Stage API | 22:43 |
lkcl | https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=b50d83f14e83aae30f52aedd030e385889a50867 | 22:43 |
lkcl | ControlBase was not being given a stage argument | 22:43 |
lkcl | which meant that manual explicit creation of p.i_data and n.o_data had to be done | 22:44 |
lkcl | that's the Stage API's job | 22:44 |
lkcl | cesar, it's perfectly valid to pass in stage=self | 22:45 |
lkcl | but you have to have an ispec() and ospec() function in the same class | 22:45 |
lkcl | (just like there now is in FSMDivCoreStage) | 22:45 |
lkcl | normally, it would be a separate class instance | 22:45 |
lkcl | passed in as an argument | 22:46 |
lkcl | whilst either way is valid, a separate class instance is what would allow us to do combinatorial Stage Chains | 22:49 |
lkcl | but it is not important for now. | 22:49 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!