Sunday, 2021-11-07

lkclVeera[m], that'll be me, as i am the only one with an arty-a7, and i've a huge number of other things to do, sorry :)12:04
lkclcesar, ha! ReservationStations2 works!13:10
lkcland i got rid of redundant wrmask13:10
lkclha! i also managed to reduce the ReservationStations FSM down to 2 cycles per RS13:17
lkcli'm currently running through test_issuer using it in "one RS" mode13:33
lkclworks fine for ALU, Logical, CR - Branch i am doing now13:33
lkclso if it works with one RS, we don't need FunctionUnitBaseSingle13:34
lkclBranch is fine13:34
lkclthe DIV FSM however _will_ need FunctionUnitBaseSingle13:35
lkcland any other FSMs13:35
lkclShiftRot is good13:37
cesarDo we actually have some multi-stage pipelined function units? Maybe for floating-point?13:37
lkclyes, i deliberately made mul a 2-stage13:37
lkclerr for some reason mul isn't in testissuer!13:38
cesarI guess it takes too long... There's a compunit unit test for it, I think.13:39
lkclthat's the mul long one13:39
lkcli'm adding it now13:40
lkcltrundle, trundle...13:40
lkclurr zzzz 40x random values per test times 10 tests zzzz13:42
lkcldone, all good!13:43
lkclok committed13:45
* lkcl running a full test just to make sure13:46
lkclcesar, i made some notes about the RSes, num_rows has to be set to 115:48
lkcland, also, i just added some Read-after-Write Hazard vectors15:48
lkclactually, err, we don't need both RaW and WaR, only need one of those15:49
lkclwill sort that15:49
* cesar is still getting familiar with the Pipeline API.16:11
cesarNo problem there, just need time.16:12
* lkcl thinking16:30
lkcl1.5 hrs until the 2nd day opentapeoutdev
lkclcesar, some signals, like "Stall" or "Exception happened" still have to be global in nature16:34
lkcland fed from InOrderIssuer by routing out of Stages into other Stages16:35
lkclwhich is a bit awkward16:35
cesarIt may be possible to isolate them in specially crafted Pipelines, manipulating ready/valid directly (not using the Pipeline API)16:39
cesar(I'm still planning an approach, considering what the Pipeline API has to offer)16:52
lkclcesar, yes, it would17:32
lkclhowever bear in mind, if we want to re-use the components later, or split down into smaller combinatorial blocks that are auto-chained together (for lower-speed ASICs)17:32
lkclthe Stage API can handle that17:32
lkcl_without_ massive rewrites17:32
cesarGot it.17:33
lkclif done as an FSM-based Stage, it is a hybrid of the two approaches17:34
lkclstill ready/valid is directly exposed17:34
lkclbut then managed by a chain of ControlBase derivatives17:34
lkclprogrammerjake, i corrected the DIV FSM, FSMDivCoreStage to properly conform to the Stage API22:43
lkclControlBase was not being given a stage argument22:43
lkclwhich meant that manual explicit creation of p.i_data and n.o_data had to be done22:44
lkclthat's the Stage API's job22:44
lkclcesar, it's perfectly valid to pass in stage=self22:45
lkclbut you have to have an ispec() and ospec() function in the same class22:45
lkcl(just like there now is in FSMDivCoreStage)22:45
lkclnormally, it would be a separate class instance22:45
lkclpassed in as an argument22:46
lkclwhilst either way is valid, a separate class instance is what would allow us to do combinatorial Stage Chains22:49
lkclbut it is not important for now.22:49

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