Monday, 2021-11-08

*** kylel1 is now known as kylel09:46
* cesar is getting familiar with the Pipeline API by playing on a sandbox.10:06
lkclcesar, i have an idea: to convert to a pipeline stage10:50
lkclthis would have the side-effect of allowing you to see how it works10:50
cesarSure. But there is plenty of examples already in nmutil. No need to touch just to show me another example... I agree though that adding handshake ports to is a good idea.11:00
lkclthe process of conversion begins to define the in and out data structures11:01
lkclwhich is a necessary step11:07
lkcldone, but, hmm, just discovered that is not terminating11:13
lkclah. that's going back to before oct 28 commit 7beae23711:15
lkclahh part of the test runner api change11:20
lkclcommit f25faf58a311:23
lkclthe change-point from running side-by-side to running completely through simulator (and waiting for KeyError) then completely through HDL11:24
lkclTestIssuer doesn't terminate in SVP64 mode11:26
lkclthat'll be a long-standing bug, previously undiscovered11:36
lkclok that's mostly converted14:46
lkclready/valid signalling on the input.14:46
lkclcore.issue_i is removed, using core.p.i_valid instead14:46
lkclcore.busy_o is removed, using ~core.p.o_ready instead14:47
lkclexc_happened (previously in TestIssuer) has moved to core.n.o_data14:47
* lkcl re-running complete test issuer all unit tests14:49
lkclpasses no problem16:37
*** tplaten <tplaten!> has left #libre-soc20:04
lkclcesar, i just altered how rdmaskn needs to be set in MultiCompUnit23:49
lkclit goes into the src latch _input_, now, rather than masks the _output_ of the src latch23:49
lkclbut, that meant that the src data would be left held on anything excluded from rdmaskn23:50
lkclwhich meant that on the next ALU request, previous data went into the ALU.  whoops :)23:50
lkclto fix that i added a reset / zero-out mechanism: when the ALU says "not busy", all the src data latches are cleared.23:51
lkclfixes it23:51
lkclnow, rdmaskn does not have to be held HI23:51
lkclit can be asserted only one clock: when issue_i is set23:51 still works23:52

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