Friday, 2021-12-10

jnthere's the rename: [amaranth-lang/amaranth-boards] whitequark b968cfa - Rename nMigen to Amaranth HDL.10:55
lkcllet's check if they did it right11:44
lkclAmaranth (previously nmigen).11:46
lkclthat's "continuity"11:46
lkclthat's also continuity11:48
lkclprogrammerjake, intriguing that others are also noting the definition of "open"13:54
octaviusAmaranth? Interesting name, I wonder if they based it off the genus of plants16:56
tplatenI'm having my first look at src/soc/experiment/, I never looked there before.18:28
tplatenonly a_busy_o and f_instr_o are connected, very simple18:34
tplatenI noticed that there are two busy signals: a_busy_o and f_busy_o, why? only one of those is used by FetchFSM.18:59
lkclyes, it's far too simple.19:23
lkclbecause i have no idea how the code written by the Minerva team works19:23
lkclit's completely undocumented - not one single comment is present in the entire 4,000 line codebase19:25
lkcloh wait, i found one!19:26
lkclso this is a guess: f_busy_o is *maybe* equivalent to n.o_ready19:30
tplatenI have begun deduplicating test_loadstore1.py19:31
tplatenthe function icache_read could be easily ported to the Minerva interface if needed19:33
tplatenI just saw that nmigen has been renamed to amaranth19:36
octaviusDoesn't look like m-labs have released any public updates about nmigen though. Their git repo is a little stale now
tplatenYears before I started working on libre-soc, I only knew migen the Milkymist Generator. The first Milkymist used a LM32 CPU from Lattice on a XILINX FPGA.19:51
octaviusThanks lkcl! Finally something clicked! I'm able to write the bitstream into the jtag bs, as well as read the output result. I'll try to use the ios keys to discern which bit of the output corresponds to which signal. This can then be used to assert signals after getting the shift register output21:17
octaviusI'll explain it better in my next bug comment, just wanted to share now21:17
lkcloctavius, hurrah :)23:02
lkclprogrammerjake, congratulations on implementing your first full instruction :)23:03
lkcllike... everything: simulator pseudocode, unit tests, formal correctness proof (which is a big deal) and HDL.23:03
lkclthat's a great achievement.23:03
octaviusCongrats programmerjake, very impressive23:12
octaviusBug posted, will try to make the test improvement tomorrow. Now should get some sleep. Good night/day23:13

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