| jn | there's the rename: [amaranth-lang/amaranth-boards] whitequark b968cfa - Rename nMigen to Amaranth HDL. | 10:55 |
|---|---|---|
| lkcl | let's check if they did it right | 11:44 |
| lkcl | Amaranth (previously nmigen). | 11:46 |
| lkcl | nope. | 11:46 |
| lkcl | that's "continuity" | 11:46 |
| lkcl | https://github.com/amaranth-lang/amaranth/commit/909a3b8be74aaf534426e64f73cc29e5bd25a8ce | 11:48 |
| lkcl | that's also continuity | 11:48 |
| lkcl | programmerjake, intriguing that others are also noting the definition of "open" | 13:54 |
| octavius | Amaranth? Interesting name, I wonder if they based it off the genus of plants | 16:56 |
| octavius | https://en.wikipedia.org/wiki/Amaranth | 16:56 |
| tplaten | I'm having my first look at src/soc/experiment/imem.py, I never looked there before. | 18:28 |
| tplaten | only a_busy_o and f_instr_o are connected, very simple | 18:34 |
| tplaten | I noticed that there are two busy signals: a_busy_o and f_busy_o, why? only one of those is used by FetchFSM. | 18:59 |
| lkcl | yes, it's far too simple. | 19:23 |
| lkcl | because i have no idea how the code written by the Minerva team works | 19:23 |
| lkcl | it's completely undocumented - not one single comment is present in the entire 4,000 line codebase | 19:25 |
| lkcl | oh wait, i found one! | 19:26 |
| lkcl | https://github.com/minerva-cpu/minerva/blob/master/minerva/units/fetch.py#L147 | 19:26 |
| lkcl | so this is a guess: f_busy_o is *maybe* equivalent to n.o_ready | 19:30 |
| tplaten | I have begun deduplicating test_loadstore1.py | 19:31 |
| tplaten | the function icache_read could be easily ported to the Minerva interface if needed | 19:33 |
| tplaten | I just saw that nmigen has been renamed to amaranth | 19:36 |
| octavius | Doesn't look like m-labs have released any public updates about nmigen though. Their git repo is a little stale now https://github.com/m-labs/nmigen | 19:47 |
| tplaten | Years before I started working on libre-soc, I only knew migen the Milkymist Generator. The first Milkymist used a LM32 CPU from Lattice on a XILINX FPGA. | 19:51 |
| octavius | Thanks lkcl! Finally something clicked! I'm able to write the bitstream into the jtag bs, as well as read the output result. I'll try to use the ios keys to discern which bit of the output corresponds to which signal. This can then be used to assert signals after getting the shift register output | 21:17 |
| octavius | I'll explain it better in my next bug comment, just wanted to share now | 21:17 |
| lkcl | octavius, hurrah :) | 23:02 |
| lkcl | programmerjake, congratulations on implementing your first full instruction :) | 23:03 |
| lkcl | like... everything: simulator pseudocode, unit tests, formal correctness proof (which is a big deal) and HDL. | 23:03 |
| lkcl | that's a great achievement. | 23:03 |
| octavius | Congrats programmerjake, very impressive | 23:12 |
| octavius | Bug posted, will try to make the test improvement tomorrow. Now should get some sleep. Good night/day | 23:13 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!