Saturday, 2021-12-18

ghostmansdfrom the page it looks like "Friendship ended with nMigen, now Amaranth HDL is my best friend"12:44
lkclyou're my bestest friend in the whoole wide worrld18:10
lkclbut seriously: it's taken some time for details to emerge.  M-Labs funded whitequark and a team of friends18:10
lkclwhen users started complaining to M-Labs on their forums, whitequark quit and took the entire team with her, leaving M-Labs - the owner of the Trademark - with zero in-house expertise or capability to support their clients.18:11
lkclthat's extremely serious, and recognised as precisely the circumstances for which Trademark Law was created18:12
lkclwith every action they take, the hole is getting deeper and deeper.18:13
lkclright now they are spreading defamation of M-Labs on twitter.18:13
lkclall they had to do was listen18:15
lkcli have instructions running under virtual memory, now18:15
sadoon_albader[mI don't understand this whole trademark deal18:16
sadoon_albader[mlkcl: But this is awesome18:16
lkclyes. i should do a short video about it, although it's quite mundane and hard to do, staring at gtkwave traces and a unit test18:17
lkclthe instructions load from a single cache line, which gets loaded with an OP_FETCH_FAILED to trigger the TLB load18:18
sadoon_albader[mThat's what makes me get popcorn18:18
lkcli have a couple of things to sort out for the unit test infrastructure itself18:19
lkclone more instruction has always been accidentally executed than should be18:20
lkclwhich never mattered before18:21
sadoon_albader[mI remember something funny similar to that happening with my capstone project for uni18:23
sadoon_albader[mIt was a hardware implementation of poly1305 and I think it was authenticating the message twice18:23
sadoon_albader[mI guess really the best way for me to actually learn nmigen is to try to port that project, which I completely understand, from SystemVerilog to nmigen18:24
lkclinteresting. yes that's very sensible18:24
sadoon_albader[mMy first implementation was using 8-bit registers all around and was painfully slow, took two months to write18:28
sadoon_albader[mI rewrote it all in 64-bit in 2 days and it flew. I don't remember how I managed to do it.18:28
sadoon_albader[mThat was only February this year, it feels like 3 years ago18:28
ghostmansdlkcl: src/openpower/sv/trans/ presents both bc_svstep and bc_step variables; the latter one seems to be unused. amirite that's a typo?20:27
ghostmansdalso bc_vli doesn't seem to be used20:28
ghostmansdalso, for bc/bclr: can all/st/sr/vs/etc. be used together, like sv.bc/all/st?20:32
ghostmansddoesn't seems so, but I don't see any errors on that; that's, again, for svp64.py20:32
lkclghostmansd, almost certainly, if it's unused23:13
lkcli had to do a redesign of sv.bc half way through23:13
lkclremoved a couple of things23:13
lkclghostmansd, check the table "format and fields" in
lkclbit 4 is ALL/SOME23:15
lkclbits 4 and 23 work together23:15
lkclsvstep mode has been removed23:20
lkclit turned out to be way too complex23:21
lkclthere's only CTR-test and VLset23:22
lkcl(and CTRtest+VLset)23:22

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