| ghostmansd | > https://libre-soc.org/irclog/%23libre-soc.2021-12-17.log.html#t2021-12-17T23:45:27 | 12:43 |
|---|---|---|
| ghostmansd | from the page it looks like "Friendship ended with nMigen, now Amaranth HDL is my best friend" | 12:44 |
| lkcl | you're my bestest friend in the whoole wide worrld | 18:10 |
| lkcl | but seriously: it's taken some time for details to emerge. M-Labs funded whitequark and a team of friends | 18:10 |
| lkcl | when users started complaining to M-Labs on their forums, whitequark quit and took the entire team with her, leaving M-Labs - the owner of the Trademark - with zero in-house expertise or capability to support their clients. | 18:11 |
| lkcl | that's extremely serious, and recognised as precisely the circumstances for which Trademark Law was created | 18:12 |
| lkcl | with every action they take, the hole is getting deeper and deeper. | 18:13 |
| lkcl | right now they are spreading defamation of M-Labs on twitter. | 18:13 |
| lkcl | all they had to do was listen | 18:15 |
| lkcl | anyway. | 18:15 |
| lkcl | i have instructions running under virtual memory, now | 18:15 |
| sadoon_albader[m | I don't understand this whole trademark deal | 18:16 |
| sadoon_albader[m | lkcl: But this is awesome | 18:16 |
| lkcl | yes. i should do a short video about it, although it's quite mundane and hard to do, staring at gtkwave traces and a unit test | 18:17 |
| sadoon_albader[m | Mundane? | 18:18 |
| lkcl | the instructions load from a single cache line, which gets loaded with an OP_FETCH_FAILED to trigger the TLB load | 18:18 |
| sadoon_albader[m | That's what makes me get popcorn | 18:18 |
| lkcl | :) | 18:18 |
| lkcl | i have a couple of things to sort out for the unit test infrastructure itself | 18:19 |
| lkcl | one more instruction has always been accidentally executed than should be | 18:20 |
| lkcl | which never mattered before | 18:21 |
| sadoon_albader[m | I remember something funny similar to that happening with my capstone project for uni | 18:23 |
| sadoon_albader[m | It was a hardware implementation of poly1305 and I think it was authenticating the message twice | 18:23 |
| sadoon_albader[m | I guess really the best way for me to actually learn nmigen is to try to port that project, which I completely understand, from SystemVerilog to nmigen | 18:24 |
| lkcl | interesting. yes that's very sensible | 18:24 |
| sadoon_albader[m | My first implementation was using 8-bit registers all around and was painfully slow, took two months to write | 18:28 |
| sadoon_albader[m | I rewrote it all in 64-bit in 2 days and it flew. I don't remember how I managed to do it. | 18:28 |
| sadoon_albader[m | That was only February this year, it feels like 3 years ago | 18:28 |
| ghostmansd | lkcl: src/openpower/sv/trans/svp64.py presents both bc_svstep and bc_step variables; the latter one seems to be unused. amirite that's a typo? | 20:27 |
| ghostmansd | also bc_vli doesn't seem to be used | 20:28 |
| ghostmansd | also, for bc/bclr: can all/st/sr/vs/etc. be used together, like sv.bc/all/st? | 20:32 |
| ghostmansd | doesn't seems so, but I don't see any errors on that; that's, again, for svp64.py | 20:32 |
| lkcl | ghostmansd, almost certainly, if it's unused | 23:13 |
| lkcl | i had to do a redesign of sv.bc half way through | 23:13 |
| lkcl | removed a couple of things | 23:13 |
| lkcl | ghostmansd, check the table "format and fields" in https://libre-soc.org/openpower/sv/branches/ | 23:14 |
| lkcl | (MSB0-mental-order...) | 23:15 |
| lkcl | bit 4 is ALL/SOME | 23:15 |
| lkcl | bits 4 and 23 work together | 23:15 |
| lkcl | svstep mode has been removed | 23:20 |
| lkcl | it turned out to be way too complex | 23:21 |
| lkcl | there's only CTR-test and VLset | 23:22 |
| lkcl | (and CTRtest+VLset) | 23:22 |
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