Thursday, 2022-01-06

lkcldoh missed tlbsync and wait as well00:05
lkclthis is the kind of thing that save/restore of verilator state won't help with unfortunately00:08
lkcladding these extra instructions even as NOPs drastically alters the HDL, which in turn alters the c++ simulation, and wark00:09
lkclif i could extract (and restore) registers and memory and the D-Cache/I-Cache TLB entries that might do the trick00:10
lkcloff we go agaaaain...00:10
programmerjakejust noticed a lot of the bitmanip ops have fields for RA, RB, and RC, but not RT...even though a lot don't need 3 inputs, but they all need an output04:19
programmerjake| NN | RA | RB  | RC  | 0  | 01    | 0010 110 |Rc| grev |04:19
programmerjakeadded todos to the wiki, can be fixed later04:33
lkclargh i'm going to have to deal with mis-aligned LD/STs.14:15
lkclalthough the linux kernel is catching 0x600 there's no guarantee it's doing the right thing.14:15
lkclbecause 0x600 is supposed to be for page-faulting misalignments14:15
programmerjakerun a program under linux and test it...maybe easier than adding support15:47
lkclit's interfering with running the diffs15:48
lkclthere's several hundred.15:48
lkclfor now i'm going to assume they're successful15:48
lkcldiff is exiting, it can't cope with the size of the files15:48
programmerjakecan you disable unaligned memory access on microwatt?15:49
programmerjaketry's binary diff15:51
programmerjakeit may work better on large files15:51
lkcli'd need to do a full rebuild of the linux kernel and of buildroot15:52
programmerjakei meant disable in the see if linux does sw unaligned access emulation and so you get identical instruction traces15:54
lkclah yeah interesting15:54
programmerjakespecifically w/o rebuilding linux15:54
lkclit's a good idea - likely to take me a long time though15:55
lkclthe state machine in loadstore1.vhdl is quite complex15:55
programmerjakeask paul, he likely would know if there's an easy way to disable it...tho you'd have to wait for him to wake up and he may still be on vacation15:56
lkclyes he's not back until at least the 3rd week of january.15:56
programmerjakemaybe ask on irc, see if anyone knows16:00
programmerjakehmm, afaict if you change to just check misaligned, it'll likely always generate misaligned exceptions (except for lq, the logic for that is right underneath)16:07
programmerjakeseems worth trying imho16:07
lkclok diff has actually worked, let me review it16:08
programmerjakelkcl also, when you have time, can you review and add funding to
lkclit's on a different grant, which has been approved, but i need to find time to write the Schedule A (milestones) and then NLnet need to approve it16:14
lkcluse the crypto from bee for now16:15
programmerjakeoh, also, idk if you saw, but bee joined irc via matrix, tho iirc he was having some issues with decred's matrix server connecting to libera's server16:17
lkclyes i saw16:17
* lkcl waves to bee[m] 16:17
programmerjakeso he may not be able to talk/see anything16:18
lkclyeah you have to register on libera in order to be able to talk16:19
lkclotherwise it's a perfect way for spammers to flood thousands of channels16:19
programmerjakei sent him a link to the irclog for your messages via PM, just in case he can't see anything still16:22
programmerjakehmm, when i tried creating a new test matrix acct, it worked for talking on iirc16:24
programmerjakewebchat i know works without registering16:24
lkclyes, but you can't talk.16:30
lkcl(not unless you use a nick that you have registered)16:30
lkclbee stopped using email, and the libera registration i believe requires an email address.16:31
lkclno email address, no registration.  no registration, no talking.16:31
lkclemail is the base Lowest Common Denominator16:33
*** programmerjake-i <programmerjake-i!~programme@2600:6c54:7600:34a:7c06:2439:7e6e:cc27> has left #libre-soc16:34
programmerjake@lkcl ^ unregistered person talking via webchat16:34
lkclah interesting16:34
lkclok so that's not it16:34
programmerjakemaybe it is it, but libera just whitelists their own webchat and accounts, bee's account is at instead16:36
lkclah ha!17:00
lkcl+                          wr @ 000b37a1 do fffffff800000000 sel f0 ........17:00
lkcl-                          wr @ 000b37a1 do fffffff8ffffffff sel f0 ........17:00
lkcldrat, nope, the lower bits ffffffff are masked-out17:01
lkclnot helping to have that in the diffs, though17:04
lkclmhrrrrmm... i'm noticing a lot of cache misses, and found that i'd halved the number of lines in a cache17:11
lkclthat could be mis-matching against the devicetree settings i-cache-block-size = <64>;17:12
lkclprogrammerjake, oh btw i thought of a potential thing to test in python17:14
lkclvariable = "fred"; """the docstring comment"""17:14
lkclnotice the semicolon :)17:14
lkcltook me a while to think that one through, but i think it's a nice compromise17:16
lkclif it works17:16
programmerjakehmm, vscode may autoformat that to be on separate which case that'd be a no-go cuz I'm not trying to work around my autoformatter17:16
programmerjakei have it set to autoformat on save17:16
lkcldeep joy :)17:16
lkclha, apparently, just put a space after it?17:17
lkclcache line size increased17:19
programmerjakeit's not linting that i have an issue with (cuz every other line of our code triggers a lint for me anyway --- our code's a mess), it's the autoformatter maybe automatically converting 1 line to 2 lines17:19
* lkcl rerunning dtbImage, only 1 hour to go :)17:19
* lkcl waves to tplaten17:29
* lkcl currently running the dtbImage.microwatt image under microwatt-verilator with a libresoc (external) core, external_core_top.v 17:30
lkcl672,000 instructions executed so far in the past 5 or so minutes, there are another 12.5 million to go17:31
lkcli have doubled the size of dcache and icache LINE_SIZE17:32
lkclwhich means it *should* now properly match against the devicetree entries in microwatt.dts17:33
octaviuslkcl, I had thoughts about the I/O bank muxing block. I drew a diagram of the single I/O mux block, and how this block can be chained together to increase number of banks. Uploaded it here (will modify and upload to the wiki later as required):
octaviusI'm guessing that the block is insufficient because the bank select signal can't be driven the JTAG BS chain17:36
lkclyyeah this is the bit that's tricky.17:39
lkclyes, the bank-select will have to be its own special JTAG shift-register17:40
octaviusLuckily, only the bank select signals need to be hooked in, as the inputs/outputs can be tested by driving the functions17:40
lkclbut first, before even hooking it into JTAG, we need a GPIO mux system *at all* - one that has absolutely nothing to do with JTAG whatsoever17:42
lkcland it needs to be controllable via "CSRs", which then are addressable on a wishbone bus17:42
lkclwhich involves i think nmigen-stdio (or wherever CSRs are defined)17:43
lkclthe problem is, none of this is properly documented.17:43
lkclyou have to *infer* how to set up and use the CSRs to create wishbone-memory-mappable peripherals, by reading the source code of e.g. lambdasoc17:44
lkclbut yes, the muxing block (top left) looks good17:45
lkclwhen doing the registers, it's really important to bear in mind that each GPIO setting has to be in the same 8-bit memory-mapped register17:49
lkclas in: that should be an atomic operation17:49
lkclthe last thing you want is to have to write 8 bits of memory to set the pin direction17:50
lkclthen *another* 8 bits to set the IO bank 0 1 2 3 4 5 6 or 717:50
lkclthis would cause output (or input) glitches17:50
octaviusSo one CSR for both directions, and bank select?17:51
lkclnot quite17:52
lkclmore that when you select the wires which go to the thing-that-sets-direction and thing-that-sets-bank-select17:52
lkclthey *must* come from the same byte, for each of the IO pads17:53
lkclyou can't have IO pad GPIO5 being direction-set from byte 2 of a CSR17:53
lkclbut its bank-select from byte 117:53
lkclit *has* to be *both* from the same byte17:53
lkcland the reason is not obvious17:54
lkclit's because although you might create a 64-bit CSR and think, "huh, there's no problem there, everyone's going to write 64-bit data to that, right?"17:54
lkcla wishbone arbiter could *split* that17:54
lkclfunnel sorry17:55
lkclcould split that down even into single-byte writes17:55
lkclso you *have* to make sure that each individual IO pad has its settings from the same byte17:56
lkclassuming say a 64-bit CSR, GPIO pad 0 could be in byte 017:56
lkclGPIO pad 1 from byte 117:56
lkclGPIO pad 7 from byte 717:56
lkclbut you must NOT put17:56
lkclGPIO pads 0-7 direction-setting into byte 017:56
lkcletc. etc.17:57
lkclthe first simplest task would be to create a GPIO-based CSR-thing allowing the IO direction only to be set17:58
lkcl(from bit 0 of any given byte)17:58
lkcland to be able to read/write IO pads over wishbone17:58
lkclreminder - again - absolutely nothing to do with JTAG whatsoever17:58
lkcli did actually write a very dumb GPIO thing already, i wonder where it is...17:59
lkclah ha!17:59
lkclit's very wasteful of the memory-space. no "packing" at all18:03
tplatenI read the last mail about branches, I"ll create one.18:05
tplatenI had a look at microwatt-linux-5.7-verilator-boot-buildroot.txt18:12
lkclif you want to try running this, there aren't currently any instructions18:20
lkcllet me find the ones online that i started from18:21
lkclso you need joel's microwatt-5.718:21
lkcland you can just use wget to grab the builtroot from ozlabs18:22
lkclbear in mind that 4 million instructions has taken about 1/2 an hour18:22
lkcland it's still in the middle of the 3rd line of output you can see on the screenshots18:23
lkclAllocating 0x5fb320 bytes for kernel...18:23
lkcland you need the patches to microwatt-5.7 linux kernel that are included here18:24
lkcldrat, no they're not 1 sec18:25
lkcladd a new option UNCOMPRESSED18:26
lkclchange clock frequency to 50 mhz18:26
tplatenI've once build joel's microwatt-5.7 and downloaded the builtroot from ozlabs.18:29
tplatenThen I ran that in a chroot on my Talos II natively18:30
octaviuslkcl, not sure I understand exact topology of the GPIO block.18:33
octaviusAm I correct in that you want the bank to be individually selectable for each GPIO?18:33
octaviusFor example, gpio0 to bank2, gpio1 to bank0, gpio2 to bank3 etc.18:33
octaviusOr are all the individual GPIOs expected to be on the same bank?18:33
octaviusThen for the settings, by "thing-that-sets-direction" do you mean the particular gpio is an input or output?18:33
lkclthe decision of what gpio to what bank is not ours to make18:46
lkclwe are designing something that must allow *users* to make that decision18:46
lkclwhere "we just happen to be one such user"18:46
lkcltplaten, nice!18:46
octaviusSo should the chip have a completely flexible function to pad assignment (any gpio can connect to any pad)? I don't understand what the topology of the banks you expect to have. From my block design, the bank allocation is *fixed* (which I guess is NOT what is expected of the chip)18:49
lkclyes there should be a way-to-specify-the-naming-relationship18:54
lkclsuch that people do not go "oh fer god's sake, i'm forced to name GPIO0 according to some stupid hard-coded numbering"18:54
lkcl"which has nothing to do with the customer's pre-defined (set) requirements"18:55
octaviusBut we can't possibly fit the logic that assigns gpios to any of the pins on the chip? That would surely take too much logic?18:55
lkclthis is not a routing issue in the ASIC, it's an API issue in python18:56
octaviusAre we not describing the ASIC?18:56
octaviusWhat's the advantage of an API that doesn't correspond to the ASIC's bank select?18:57
lkclyes... and there must be a mapping from the public-names-of-the-pins onto the-number-behind-the-address-used-on-the-register18:57
lkcllook at simple_gpio.py18:57
*** tplaten <tplaten!> has left #libre-soc18:57
lkcldo you see any evidence of "naming"?18:57
lkclthere isn't any, is there?18:58
lkclit's just a "bank" of GPIO where the numbers on that GPIO are 0 to N-118:58
octaviusNo, I see the address numbers corresponding to the gpios (addr 0 is gpio0, addr 1 gpio1, etc.)18:58
lkclthis is a construct in your mind that you have created18:59
octaviusSo it doesn't exist?18:59
octaviusThat's what the sim shows18:59
lkclanyone may choose instead that the first 8 GPIOs are in fact GPIO Bank A 0-7 and the second-addressed 8 GPIOs are GPIO Bank B 0-718:59
lkclor, if they do a BGA (which is a 2D grid), they may decide that pad number N20 N21 N22 N23 are the first 4, 0-319:00
octavius"anyone may choose", choose where? This is the RTL generator which eventually produce an ASIC19:01
lkcland G6 G7 G8 G9 are 4-719:01
lkclin *their* specification, which *they* write, *not* us19:01
lkclit is a very simple level of indirection.  a dictionary would suffice19:01
lkclor one of those Platform Resources19:02
lkclbut we *must* not dictate to them, "YOU MUST CALL THIS PLATFORM RESOURCE GPIO0 OR ELSE"19:02
lkclwe have to let *them* decide the names of the Platform Resource(s)19:03
lkclit is much simpler than you are thinking it is19:03
octaviusI think I'm at least understanding a little. No arbitrary names.19:03
lkclthis has absolutely nothing to do with dynamic routing19:03
lkclthat would be stupid19:03
lkclto have some HDL that routes GPIO-Pad-A0 to any-GPIO-number-you-damn-well-choose19:04
lkclthat would be insane19:04
lkclthey have to be able to *specify* the name-to-number relationship19:04
lkclwhich is very simple and very straightforward19:04
lkclfar simpler than you are thinking "It Must Be Difficult Or Hard"19:04
lkcl"<octavius> No, I see the address numbers corresponding to the gpios (addr 0 is gpio0, addr 1 gpio1, etc.)"19:05
lkclit _is_ like that... but those names "gpio0", "gpio1" ....19:06
lkclthey are *internal* names that *you* have given them, for your convenience to be able to refer to them19:06
lkclthere must be some *public* names that can be specified via e.g. "a Platform Resource"19:06
octaviusSo instead it's just a dictionary with a variable number of elements (gpios)19:07
lkclwhere "The name in the Platform Resource" refers to "the thing you call inside *your* mind, gpio0"19:07
lkclwell, there's a couple of options here19:08
lkcl1) the Platform Resource MUST specify a full list of numbered GPIO that MUST be connected ONLY and DIRECTLY to a GPIO bank (in TOTAL)"19:08
lkclif the length is 16 then the GPIO bank (like MUST be EXACTLY 16 long19:09
lkcl2) it is permitted to connect SUBSETs of the Platform Resource to SEPARATE instances19:09
lkcle.g. the first 8 pins of Platform Resource(GPIOA-16) are connected to one instance of simple_gpio.py19:10
lkcland the 2nd 8 to another instance19:10
lkclstart to see why forcing the relationship inside the source code might not be such a good idea?19:11
octaviusSo where is the bank select logic fitting into this?19:11
lkclat this point it's not19:11
lkclstart small19:11
lkclwork incrementally19:11
octaviusSo in my version of "simple_gpio" there will simply be a parameter "bank select" which won't be used, but perhaps available as an output?19:12
lkclthe next phase once you have a (only barely) more sophisticated version of would be to add bank-select19:12
lkclyou mean, as an input, but yes.19:12
octaviusNah, I thought the user specifies the bank select via WB CSR?19:13
lkclyes, which means you need to write to the wishbone bus, which means it is an input19:13
octaviusSo the bank select would be an output to a mux bloc19:13
lkcl(from the perspective of the wishbone bus)19:13
lkclit would be an output *to* the mux block, yes.19:13
lkcli see what you mean19:13
lkclbut remember that it needs to be possible to read the settings as well (to find out what the current setting is)19:14
lkclbut we are getting ahead, here19:14
octaviusStart with the simple_gpio19:14
octaviusWhere should a copy this file, pinmux repo?19:14
lkclyes, good idea19:15
octaviusI don't have write access to anything else XD19:15
lkcllet's sort that out when you need it.19:15
lkclyou have write-access to the wiki, soc, pinmux and... dev-env-setup19:16
lkclif you can add a register (use sync to set it) which allows the direction to be set, and also add another for output-enable19:16
octavius"you have write-access to the wiki, soc, pinmux and... dev-env-setup" True19:17
lkclthat will allow any tri-stated IO pad to be turned into an input, output or bi-directional19:17
lkclit means actually every IO pad is bi-directional, but hey19:18
octaviusI guess some of the pads may be simplified during synthesis though? (If we decide to hardwire one of RGMII interfaces etc.)19:19
lkclnow you're getting it19:19
lkclDDR3/4/5 are good candidates for that, on proprietary SoCs19:20
lkclbecause trying to route timing-sensitive / impedance-sensitive pads through a MUX would be damn stupid19:21
octaviusYes, I thought so too19:21
lkclfrick, frick, frick i just wasted an hour by pressing Ctrl-C on the simulator after mis-reading the dump trace19:21
lkclit had got to here19:21
lkclFinalizing device tree... flat tree at 0xbd4c8019:22
lkcland i thought that it had got stuck in a loop, when in fact it was initialising memory to zero19:22
* lkcl re-running19:22
octavius"by pressing Ctrl-C on the simulator" I feel your pain...19:24
octaviusBtw, soon I'll be getting an OBD2 scanner. Planning to do diagnostics >:)19:34
lkcl[    0.000000] printk: bootconsole [udbg0] enabled21:23
lkcl -> early_setup(), dt_ptr: 0xbd4c8021:23
lkclno 0x700 exception yet, a good sign21:24
lkcl[    0.000000] dt-cpu-ftrs: setup for ISA 300021:35
lkcli think the 0x700 exception happened some time around... when the info on the MMU was being reported.21:37
lkcl                          rd @ 0007d900 di 6d6d006f74707972 sel ff rypto.mm21:38
lkcl                          rd @ 0007d901 di 6d00687361682d75 sel ff u.hash.m21:38
lkcl                          rd @ 0007d902 di 78696461722d756d sel ff mu.radix21:38
lkclthat looks like reading of device-tree entries21:38
lkcl[    0.000000] dt-cpu-ftrs: final cpu/mmu features = 0x00000087800391e1 0x3c00604121:41
lkcloh ha ha very funny. i should have spotted this the first time23:34
lkcl[    0.000000] Page orders: linear mapping = 24, virtual = 12, io = 12, vmemmap = 1223:34
lkcl[    0.000000] hash-mmu: Partition table (____ptrval____)23:34
lkcl[    0.000000] hash-mmu: Initializing hash mmu with SLB23:34
lkclwhere the microwatt-boot says "radix-mmu"23:34

Generated by 2.17.1 by Marius Gedminas - find it at!