Friday, 2022-01-07

lkclok so the device-tree entry "ibm,architecture-vec-5" is not being recognised, hmmm12:31
lkclbecause the text is endian-inverted, "hcra.mbi" instead of "ibm.arch" hmmm12:57
programmerjakeapparently linux doesn't support misaligned exceptions on LE (maybe for some subset of conditions):
programmerjakecalled by 0x600 exception handler15:54
lkclmy reading of that is the other way round due to the !=16:39
lkclif processor *not* in LE mode, and LE-is-not-an-available-feature16:39
lkclwhich would tend to suggest it's emulation of LE mode on BE-only-systems that is not available16:39
programmerjakemy reading of it is the text of the comment16:40
lkclif ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {16:40
lkclwhen MSR.LE is set, this test will fail16:40
lkclwhen the kernel's endian-ness is not equal to the processor's-current-endianness16:41
lkclthat's more like it16:41
lkclbut the circumstances of execution are:16:41
lkcl* MSR.LE is true and16:41
lkcl* MSR_KERNEL - the options by which the kernel is compiled - are also true16:42
lkcltherefore this test will fail16:42
lkcland lines 315-318 will not be executed16:42
programmerjakein any case, it indicates we probably need correct misaligned ld/st handling in hw16:42
lkclsigh yes.16:42
klyswoah no misaligned ld/st?  yeah do that20:49
lkclklys, it's complicated. the initial idea was to have an interface (called PortInterface) with a splitter21:28
lkclthat could create a *pair* of requests (each with their own PortInterface) that were merged by the splitter21:29
lkcland then to have multiple of them21:29
lkclthis for multi-issue execution where between 6 and 8 wide issue would result in between 12 to 16 requests21:30
lkclthat then funnel down to dual 128-bit-wide memory buses21:30
lkclmicrowatt on the other hand has a single 64-bit wishbone bus21:31
lkcland the initial implementation, being based on microwatt, therefore only has21:33
lkclQTY 1 (1) LoadStore interface21:33
lkclQTY 1 (1) 64-bit wishbone interface21:33
lkcltherefore, any 64-bit non-aligned requests *have* to be split into a pair of non-atomic sequential LD/STs.21:34
lkclthe initial ASIC avoided the problem entirely21:35
lkclthe Power ISA spec does not actually permit that except on page-boundaries21:35

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