| lkcl | ok so the device-tree entry "ibm,architecture-vec-5" is not being recognised, hmmm | 12:31 |
|---|---|---|
| lkcl | because the text is endian-inverted, "hcra.mbi" instead of "ibm.arch" hmmm | 12:57 |
| programmerjake | apparently linux doesn't support misaligned exceptions on LE (maybe for some subset of conditions): https://github.com/torvalds/linux/blob/fe91c4725aeed35023ba4f7a1e1adfebb6878c23/arch/powerpc/kernel/align.c#L314 | 15:54 |
| programmerjake | called by 0x600 exception handler | 15:54 |
| lkcl | my reading of that is the other way round due to the != | 16:39 |
| lkcl | if processor *not* in LE mode, and LE-is-not-an-available-feature | 16:39 |
| lkcl | which would tend to suggest it's emulation of LE mode on BE-only-systems that is not available | 16:39 |
| programmerjake | my reading of it is the text of the comment | 16:40 |
| lkcl | if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) { | 16:40 |
| lkcl | when MSR.LE is set, this test will fail | 16:40 |
| lkcl | or | 16:41 |
| lkcl | when the kernel's endian-ness is not equal to the processor's-current-endianness | 16:41 |
| lkcl | that's more like it | 16:41 |
| lkcl | but the circumstances of execution are: | 16:41 |
| lkcl | * MSR.LE is true and | 16:41 |
| lkcl | * MSR_KERNEL - the options by which the kernel is compiled - are also true | 16:42 |
| lkcl | therefore this test will fail | 16:42 |
| lkcl | and lines 315-318 will not be executed | 16:42 |
| programmerjake | in any case, it indicates we probably need correct misaligned ld/st handling in hw | 16:42 |
| lkcl | sigh yes. | 16:42 |
| klys | woah no misaligned ld/st? yeah do that | 20:49 |
| klys | imo | 20:49 |
| lkcl | klys, it's complicated. the initial idea was to have an interface (called PortInterface) with a splitter | 21:28 |
| lkcl | that could create a *pair* of requests (each with their own PortInterface) that were merged by the splitter | 21:29 |
| lkcl | and then to have multiple of them | 21:29 |
| lkcl | this for multi-issue execution where between 6 and 8 wide issue would result in between 12 to 16 requests | 21:30 |
| lkcl | that then funnel down to dual 128-bit-wide memory buses | 21:30 |
| lkcl | microwatt on the other hand has a single 64-bit wishbone bus | 21:31 |
| lkcl | and the initial implementation, being based on microwatt, therefore only has | 21:33 |
| lkcl | QTY 1 (1) LoadStore interface | 21:33 |
| lkcl | QTY 1 (1) 64-bit wishbone interface | 21:33 |
| lkcl | therefore, any 64-bit non-aligned requests *have* to be split into a pair of non-atomic sequential LD/STs. | 21:34 |
| lkcl | the initial ASIC avoided the problem entirely | 21:35 |
| lkcl | the Power ISA spec does not actually permit that except on page-boundaries | 21:35 |
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