| bee[m] | test | 02:41 |
|---|---|---|
| bee[m] | I think it works? Hi all :) | 02:45 |
| tplaten | I had a quick look at the load misalign code, store is more complicated here. | 17:02 |
| tplaten | But I first think how to implement load 8 bytes at *mis*-aligned address which is NOT within the page. | 17:05 |
| lkcl | yes | 17:26 |
| lkcl | it is | 17:26 |
| lkcl | ok that's the one that has to throw a pagefault | 17:27 |
| lkcl | i am currently adding mmu test5 to show it | 17:27 |
| lkcl | (git pull) | 17:27 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=663a9ac191c978b567681d0de59f1f82cc876be9 | 17:28 |
| lkcl | what is currently happening is that a LDST pagefault is occurring on the *first* of the requests, which should not be happening | 17:29 |
| lkcl | tplaten: test_loadstore1_mmu_test5 is working fine except DAR is 0x3a0005 not 0x3a0000 | 18:08 |
| lkcl | mmu.bin | 18:08 |
| lkcl | test 05:store PTE @ 0000000000013cf8 => c00000000000b186 FAIL 3 DAR=00000000003a0005 DSISR=0000000040000000 | 18:08 |
| lkcl | that's because the MMU_LOOKUP going to the MMU is a request to look up the PTE for 0x3a0005 (which it should be doing) | 18:09 |
| lkcl | but i don't quite understand why the rounding-down is not being reported | 18:10 |
| lkcl | https://github.com/antonblanchard/microwatt/blob/7fa7b45faa17950de44591f7a73722fdf8a87385/tests/mmu/mmu.c#L317 | 18:10 |
| lkcl | i mean, like, i can't even find any evidence in mmu.vhdl or loadstore1.vhdl of the rounding that's clearly occurring! | 18:11 |
| lkcl | unless.... | 18:12 |
| lkcl | hmmm this is really tricky | 18:18 |
| *** tplaten <tplaten!~isengaara@p200300ddff1536002e094dfffe000232.dip0.t-ipconnect.de> has left #libre-soc | 18:25 | |
| lkcl | ahh i think it might not matter | 19:08 |
| * lkcl started re-running linux-5.7 2 hours ago after adding misaligned LDs (not STs) | 20:29 | |
| lkcl | so far no 0x600 exception | 20:29 |
| lkcl | alriiiight, that fixed it | 20:54 |
| lkcl | dtb entry ibm,architecture-vec-5 was successfully found | 20:54 |
| lkcl | so it's a linux kernel bug and/or a... something-to-do-with-0x600 bug | 20:54 |
| lkcl | perhaps DAR is not being set correctly or something | 20:55 |
| lkcl | should now progress to setting up the radix mmu | 20:55 |
| octavius | lkcl, now that you asked me to document my code, I'm embarrassed to admit I finally understand Resources, ASICPlatform, and how the HDL just sees standard peripheral names (and not caring about the IO pads) | 21:09 |
| lkcl | :) | 21:10 |
| lkcl | yyep | 21:10 |
| lkcl | it was intended so that you could write HDL for any FPGA | 21:11 |
| lkcl | no need to know or care about | 21:11 |
| lkcl | what the HDL is actually running on | 21:11 |
| octavius | yeah | 21:11 |
| lkcl | we are simply going, "well, we don't care that it's an ASIC" | 21:11 |
| lkcl | [ 0.000000] radix-mmu: Mapped 0x0000000000000000-0x0000000000600000 with 2.00 MiB pages (exec) | 21:16 |
| lkcl | [ 0.000000] radix-mmu: Mapped 0x0000000000600000-0x0000000010000000 with 2.00 MiB pages | 21:16 |
| lkcl | currently initialising those pages to zero | 21:16 |
| octavius | How long does that take? | 21:17 |
| lkcl | which sounds perfectly reasonable but | 21:17 |
| lkcl | ooo maybe... about half an hour to an hour? | 21:17 |
| octavius | XD | 21:17 |
| octavius | Why can't you just create an empty area of memory to begin with? Or is this part of the boot process that must be simulated? | 21:18 |
| lkcl | it's executing i think... 1,000 instructions per second? | 21:20 |
| lkcl | dang, the python-based simulator i think is quicker than that | 21:21 |
| octavius | lkcl, I'm looking at your JTAG wireup example on the docs/pinmux page, and I'm not sure these two are correct: | 21:44 |
| octavius | m.d.comb += uart.tx.eq(utx.pad.i) # transmit JTAG to pad | 21:44 |
| octavius | m.d.comb += utx.pad.o.eq(uart.rx) # pass rx to JTAG | 21:44 |
| octavius | Looks to me like it should be the other way round (pad.o is an output, so connects to tx) | 21:44 |
| lkcl | uart is the function that generates the signal. therefore, uart.tx is the driver | 21:45 |
| lkcl | so yes, wrong way round | 21:46 |
| octavius | Ok, I'll fix the doc | 21:46 |
| lkcl | star | 22:01 |
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