| cesar | lkcl: When you say that the design works only below some X MHz, do you mean it does not pass timing analysis, above X MHz, when you compile it? Or, it passes timing at X MHz or greater, but only gives correct output when you go below X MHz? | 20:55 |
|---|---|---|
| cesar | ... correct output from the FPGA serial port, I mean. | 20:56 |
| *** mepy_ is now known as mepy | 22:46 | |
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