| programmerjake | lkcl: mithro replied: https://github.com/SymbiFlow/f4pga-arch-defs/issues/2463#issuecomment-1065610164 | 00:15 |
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| *** alMalsamo is now known as lumberjack123 | 05:14 | |
| lkcl | well, not a "biiiig" deal, but yeah, "lanes" only makes sense at the internal-hardware-level, for hardware-architects to have a term whereby they can refer to the parallel pathways in a SIMD ALU | 09:23 |
| lkcl | with a SIMD ISA the numbering on the lanes unfortunately become synonymous with (identical to) the numbering on the elements at the ISA level | 09:24 |
| lkcl | hence the confusion. | 09:24 |
| lkcl | however for say the Broadcom VideoCore IV which can do "Virtual Elements", that's where [one of many of] the problems start | 09:25 |
| lkcl | VideoCore IV's FPU has only a 4-lane-wide internal SIMD ALU but it has a hardware-for-loop to make it *look* like it has *16* actual elements | 09:26 |
| lkcl | you issue a 16-element-wide instruction at the *ISA* level that gets broken down such that elements 0,4,8,12 are all fed to Lane 0 of the hardware, elements 1,5,9,13 to Lane 1 of the hardware.... | 09:27 |
| lkcl | programmerjake, yep, mithro's worked out that this is like "patching binaries" rather than fixing the problem at the c-source-code level. | 09:31 |
| lkcl | expecting gcc, llvm, intel-c-compiler and msvc to all re-construct a high-level programming concept after it's been compiled to assembler (or lower) | 09:43 |
| lkcl | whereas [slightly off-topic for the bug] if the symbiflow hack-in-python to morph the chain-of-carry4s into a proper carry-lookahead-tree were instead added as a yosys techmap pass, then every one of the free software P&Rs benefits, everyone has significantly less work to do, | 09:46 |
| lkcl | and, hilariously, i suspect that resource efficiency on the xilinx proprietary P&R would go up as well | 09:46 |
| lkcl | toshywoshy, openpowerbot_ needs poking with a stick on this channel, mattermost | 10:52 |
| lkcl | and #microwatt it seems. not getting through to oftc either | 10:52 |
| octavius | lkcl....guess who had forgotten his m.d.comb prefix? XD | 16:09 |
| lkcl | octavius, been there :) | 16:11 |
| octavius | That's half the fun I guess | 16:13 |
| octavius | Well, good thing is I can get on with it now | 16:14 |
| lkcl | joy and celebration. | 16:14 |
| * lkcl said in the voice of Douglas Adam's "Marvin the Paranoid Android" of course | 16:15 | |
| octavius | https://www.youtube.com/watch?v=895pIjyRUIk | 16:26 |
| lkcl | brain the size of a planet, and what have they got me doing? parking cars for a million years. | 16:31 |
| cesar | lkcl: I am creating a new file (src/soc/regfile/sram_wrapper.py). Should I put a header with licencing, copyright and sponsor information? Something like the one in src/soc/bus/external_core.py? | 20:54 |
| cesar | If so, what would be the sponsoring information for this particular work (the SRAM wrapper, bug 781)? | 21:26 |
| lkcl | cesar, yes | 21:35 |
| lkcl | same. that basically becomes the default template, now, really | 21:35 |
| cesar | Got it, thanks. | 21:36 |
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