Saturday, 2022-03-26

lkclprofessor dimitry galayko confirmed that the PLL is operational on the ls180 ASIC. he had access to a 20 mhz signal generator at the time, and will try something faster later15:00
tplatenI'm having a look of the orangecrab port of microwatt using the libre-soc core.18:24
tplatenThe external_core_top.v:262095: ERROR: Re-definition of module `\plru_2'! is caused by litedram-wrapper-l2.vhdl18:26
tplatenTestIssuerInternal or one if its submodules seems to generate the plru that conflicts with litedram_wrapper18:51
tplatenI think I have found the problem: src/soc/experiment/ is based on based on microwatt plru.vhdl and plru.vhdl is also needed by litedram-wrapper-l2.vhdl/top-orangecrab0.2.vhdl19:02
tplatenThe weird thing is that \plru_0 and \plru_1 are not redefined, how does yosys generate the numbers, is there any documentation?19:56
lkcltplaten, ahh20:06
tplatenI'll continue tomorrow20:12
lkclin this case it's not yosys generating the numbers20:13

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