| lkcl | professor dimitry galayko confirmed that the PLL is operational on the ls180 ASIC. he had access to a 20 mhz signal generator at the time, and will try something faster later | 15:00 |
|---|---|---|
| tplaten | I'm having a look of the orangecrab port of microwatt using the libre-soc core. | 18:24 |
| tplaten | The external_core_top.v:262095: ERROR: Re-definition of module `\plru_2'! is caused by litedram-wrapper-l2.vhdl | 18:26 |
| tplaten | TestIssuerInternal or one if its submodules seems to generate the plru that conflicts with litedram_wrapper | 18:51 |
| tplaten | I think I have found the problem: src/soc/experiment/plru.py is based on based on microwatt plru.vhdl and plru.vhdl is also needed by litedram-wrapper-l2.vhdl/top-orangecrab0.2.vhdl | 19:02 |
| tplaten | The weird thing is that \plru_0 and \plru_1 are not redefined, how does yosys generate the numbers, is there any documentation? | 19:56 |
| lkcl | tplaten, ahh | 20:06 |
| tplaten | I'll continue tomorrow | 20:12 |
| lkcl | in this case it's not yosys generating the numbers | 20:13 |
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