lkcl | well, what we are doing is borrowing bits from EXT01. | 14:09 |
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lkcl | EXT01 is the major opcode for Power ISA v3.1 "64-bit prefixing" | 14:09 |
lkcl | in theeooorrryy there should be some patches to binutils to add 64-bit prefixing support already | 14:09 |
lkcl | but | 14:09 |
lkcl | i don't know how they decided to do it | 14:09 |
tplaten | I now continue on the orangecrab port of ls2 | 14:10 |
lkcl | tplaten, cool | 14:10 |
tplaten | I assume that on an FPGA it boots from an SPI flash, which I will need to define first | 14:13 |
lkcl | ah no. | 14:13 |
tplaten | block ram used as rom, not sure | 14:13 |
lkcl | a program is uploaded over DFI-UTIL which happens to contain a ROM-based (BRAM-based) version of coldboot.bin | 14:14 |
lkcl | where coldboot.bin has been compiled to look, in *software*, for the SPI flash peripheral | 14:14 |
lkcl | yes BRAM is used effectively as a ROM. | 14:15 |
tplaten | I now have a look at coldboot.c, but assume that one can use hello_world for a first test instead | 14:21 |
tplaten | because currently on the orangecrab I get | 14:22 |
tplaten | ddr pins None | 14:22 |
tplaten | spiflash pins None | 14:22 |
lkcl | yes | 14:25 |
lkcl | it's a good idea. | 14:25 |
lkcl | hello_world.bin only needs BRAM and uart. | 14:26 |
lkcl | from the verilator working you shouuuld be set up with the right start address | 14:27 |
tplaten | I added SRAM (read-writeable BRAM) at 0x8000_0000 and still don't get any output from the hello world program. Something I must have forgotten. | 15:43 |
tplaten | At least the Blinky module is working on ls2 on orangecrab. | 15:50 |
tplaten | I compiled external_core_top.v with a matching --pc_reset and set BOOT_INIT_BASE to the correct address, still I do not get any UART output. | 15:58 |
tplaten | I saw that ulx3s is using 40mhz, it now works. | 18:05 |
tplaten | I get a "■ libre-soc, it works" output, now commiting the changes | 18:42 |
tplaten | Tomorrow, I'll try to get SPI flash working | 18:52 |
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