| lkcl | ooo still trying to track down what the heck is going on with timer_interrupt() | 11:58 |
|---|---|---|
| lkcl | there's a permanent loop going on where timer fires timer fires timer fires timer | 11:59 |
| programmerjake | maybe the timer is counting too fast or the timer interrupt isn't properly acknowledged or something? | 12:06 |
| lkcl | the clock frequency is only 25 mhz: really low | 12:14 |
| lkcl | that's what will work. how that influences the number of occurrences of the timer is what i'm investigating | 12:15 |
| programmerjake | well...if the timer is counting fast enough that it can trigger another interrupt before the first one ends...it's too fast even if it counts at 32khz. maybe set linux's tick rate to be >1ms? iirc it defaults to 1ms | 12:24 |
| lkcl | i'm adding + select GENERIC_CLOCKEVENTS_MIN_ADJUST | 12:28 |
| lkcl | to see if that helps | 12:28 |
| lkcl | CLOCKEVENTS is currently allowed (for powerpc) to be extremely fast | 12:29 |
| lkcl | tplaten, read the comments in the ls2.py source code regarding QSPI | 13:45 |
| lkcl | also note that the VERSA_ECP5 specifically requires the ECP5 to drive the clock line (USRMCLK) | 13:47 |
| tplaten | I had a short look at, that part | 13:51 |
| tplaten | After I found out about rcs_arctic_tern_bmc_card, I did a look at https://wiki.raptorcs.com/wiki/File:Kestrel_Demo_OCP_Virtual_2021.webm | 14:10 |
| tplaten | Yes, I saw that SPIFlashResources is different, it has cs_n="U17", clk="U16", miso="T18", mosi="U18", wp_n="R18", hold_n="N18", there is no dq0 to dq3. | 14:30 |
| lkcl | tplaten, correct. | 16:22 |
| lkcl | what about this comment | 16:23 |
| lkcl | # Override here to get FlashResource out of the way and enable Tercel | 16:23 |
| lkcl | # direct access to the SPI flash. | 16:23 |
| lkcl | # each pin needs a separate direction control | 16:23 |
| tplaten | I had a look at that, looks good. | 16:41 |
| tplaten | I came with a similar thaught, but I get a | 16:42 |
| tplaten | AttributeError: Record 'spi_0_0__dq0' does not have a field 'o_clk'. Did you mean one of: i, o, oe? | 16:42 |
| tplaten | most likely some repositories have to upgraded | 16:42 |
| lkcl | tplaten, you need to copy the section in versa_ecp5 exactly | 17:41 |
| lkcl | then make absolutely certain that you set the spi0_is_lattice_ecp5_clk = True flag | 17:42 |
| lkcl | if you do not set xdr on the platform request it will *not* create the required o_clk field | 17:42 |
| lkcl | there's a chain of things that you have to get right, otherwise it goes to hell | 17:43 |
| lkcl | https://git.libre-soc.org/?p=ls2.git;a=blob;f=src/ls2.py;hb=HEAD#l935 | 17:44 |
| tplaten | the first thing I knew about: spi0_is_lattice_ecp5_clk is set to True when using the orangecrab. | 17:59 |
| tplaten | Yes, I forgot to set xdr in my code | 18:04 |
| lkcl | xdr set up phase-offset capability. | 18:18 |
| lkcl | but also it allows an IOpad to be specifically driven by a clock | 18:19 |
| lkcl | in the case of the SPI pads, that *has* to be USRMCLK | 18:19 |
| lkcl | it's a strange quirk of the ECP5, i have no clue why they did it that way. | 18:19 |
| tplaten | I know about USRMCLK, i'll do a deeper look at ls2.py tomorrow. | 18:22 |
| tplaten | When not working on libre-soc, sometimes I compose songs for which I use a synthesizer singer written in python and c++ | 18:26 |
| lkcl | wow cool! | 18:32 |
| lkcl | is it available libre-licensed somewhere? | 18:32 |
| lkcl | i always wanted to do that | 18:32 |
| tplaten | Of course, it is libre. GNU AGPL for the engine core, no copyleft for some other components. | 18:33 |
| lkcl | programmerjake was mentioning on tuesday that he did a PWM attiny85 synthesiser | 18:34 |
| lkcl | love to hear it and see how you did it | 18:34 |
| lkcl | i've looked occasionally for synthesiser python code for a while | 18:35 |
| tplaten | I also had a look at https://github.com/trcwm/Speech256 | 18:35 |
| lkcl | oOoo | 18:35 |
| tplaten | https://codeberg.org/praatloid | 18:35 |
| lkcl | http://www.sinsy.jp/ | 18:36 |
| tplaten | there are many UTAU clones and plugins written in python, not all are libre, some lack a license. I wrote my own frontend with an XML to UST converter in pure python | 18:37 |
| lkcl | holy cow, that's synthesised voice?? | 18:37 |
| tplaten | I combined Sinsy with MBROLA | 18:37 |
| tplaten | Some time ago, I will use https://pypi.org/project/nnsvs/ | 18:37 |
| lkcl | wow. just wow, that's astounding quality | 18:37 |
| tplaten | I think I could train a model with some poems from http://lkcl.net/poems/ and a melody I will write. | 18:39 |
| lkcl | i've a larger set online as well | 18:40 |
| tplaten | My fork of Sinsy has support for the English language, the original version only supports Japanese | 18:40 |
| lkcl | https://allpoetry.com/lkcl | 18:40 |
| tplaten | The I will sing those poems and record my singing | 18:41 |
| lkcl | a lot of them have a rhythm suitable for singing | 18:43 |
| ghostmansd | Good news, `sv.extsw 5.v, 3.v' already produces two insns in binutils :-) | 18:43 |
| lkcl | ghostmansd, good grief | 18:43 |
| ghostmansd | in fact, we're almost here: we have (00004005 b407657c) instead of (002f4005 b407017c) from $(sv.extsw 5.v, 3.v) | 18:44 |
| ghostmansd | but I haven't addressed rm assignment yet, and haven't yet completed the whole remap of insn | 18:45 |
| ghostmansd | so, some bits are different, still you can see the pattern :-) | 18:45 |
| lkcl | yehyeh | 18:45 |
| lkcl | that looks like the register numbering isn't correct yet | 18:46 |
| lkcl | tplaten, this dance tune is from the 1200s https://hands.com/~lkcl/Luke's_Mediaeval_Dance.mscz | 18:49 |
| lkcl | imagine a monk going through a village, hears a dance tune that he's never heard before, writes it down | 18:50 |
| lkcl | but there was no tempo or time-signatures back then because all written music was more an "aide-memoire" | 18:50 |
| lkcl | i made a best-guess as to what the timing is and it turns out to be a 3-harmony round | 18:51 |
Generated by irclog2html.py 2.17.1 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!