Wednesday, 2022-06-15

kanzurelkcl: missed that.00:04
kanzureoh nevermind. hi.00:04
lkclkanzure: there's always next week. same time. UTC 22:00. i can add you to a calendar invite reminder?04:18
lkclprogrammerjake, the openpower.util.log function has had a SILENCE_LOG environment variable for 8+ months04:19
lkcli'm... how to put it delicately... "slightly raising an eyebrow" that you are only just learning of this, and sent a message to the list04:23
lkcl"there must be less print() statements", but didn't check the source code to find that there *aren't* any04:24
lkclthey've all been replaced with a call to log()04:24
lkclthe thing that's puzzling me somewhat is that i would have expected your first reaction to have been to look at the source code searching for evidence of print() statements04:25
lkclbecause you would have found that there aren't any04:26
programmerjakewell, I'm raising an eyebrow that you didn't check... openpower-isa.git:05:11
programmerjake`grep '^\W*print *(' -R . | wc -l`05:11
programmerjakethere are >3x as many print calls as log calls -- 301 log calls vs. 1080 print calls05:13
programmerjakeas of commit 32b94e99b7e0f863a7f6c5eeb1d8c6dff38fcf31 Date:   Tue Jun 14 15:13:43 2022 +010005:13
programmerjakein any case...gitlab-ci needs to have less output lines for it to be readily useful when a build fails05:15
*** kylel1 is now known as kylel07:07
lkclprogrammerjake: then set SILENCELOG=1 as an environment variable12:06
lkcl8+ months ago i focussed on those print() statements that helped lauri.12:15
lkclthat was focussed on pysvp64sim. i left everything else12:15
ghostmansd[m]Hi folks, a quick question: when does OPF meeting takes place?14:39
ghostmansd[m]And could someone PM me the credentials so that I'll be able to visit it?14:39
octaviusghostmansd[m], same link as yesterday, same time14:53
ghostmansd[m]Ah OK so these two meeting are once per two weeks?15:02
ghostmansd[m]I have some event in calendar sent by Luke, but it shows that meeting happens on Thursday...15:03
octaviusghostman[m], the tuesday meeting is once a week16:13
octaviusthe open power meeting is every two weeks16:14
ghostmansd[m]Ok, so OpenPower meeting is at Thursday, right?16:21
octaviusthird time lucky ghostmansd[m] :P16:40
octaviusThe OpenPower meeting is today (wednesday)16:40
octaviusActually wait, by the moscow timezone, yeah16:41
octaviusI should have specified the timezone, sorry16:41
octaviusAlso, just checked my past emails, you're included on there, check that it's not in spam16:44
octaviuslkcl, can you send out today's meeting email?16:44
lkcloctavius, yep on it16:49
lkclghostmansd[m], you're on GMT+3, the meeting's at GMT 21:00, therefore it's actually midnight local time for you (just like yesterday) but strictly speaking it's 00:00 *thursday* aka 24:00 *wednesday*17:04
lkcl4 hours from now, basically :)17:04
lkclVeera[m], are you happy to help add cvc5 to the yosys script?;a=blob;f=hdl-tools-yosys;hb=HEAD17:06
programmerjakeif you want to work on that, I already figured out building it:
programmerjakelkcl: i am planning on adding that myself later if no one else does that first17:15
programmerjakeas part of changing our build scripts to work with smtlib2 nmigen17:16
programmerjakeI'm currently blocked on:
programmerjakeso am working on gitlab-ci server stuff meanwhile17:17
ghostmansd[m]Perfect folks, thanks for the link! I'll try joining today (or, well, on Thursday).17:18
ghostmansdlkcl, since we're going to publish setvl, svstep, svshape and svremap, I had to rebase the branch so that these appear first20:05
ghostmansdbut there're worse news, I think we should provide binutils tests for each of these20:06
ghostmansdI'll raise the task about it; these are not show-stoppers and can indeed be already published to review, as long as they have tests20:07
ghostmansdthe latter conclusion is my assumption, since all commits from Alan I had a chance to look at, unsurprisingly come with tests20:08
ghostmansdlkcl, would it be OK if I raise task on these four, or you'd rather prefer to see one giant task about binutils tests?20:09
ghostmansdor, maybe, both? a giant task on binutils tests and subtask about these 4?20:09
ghostmansdFWIW, draft insns already have tests, since I intended to publish these from the very beginning :-)20:10
lkclghostmansd, yes good call on tests.20:35
lkclhmmm we're at EUR 3275 on 577
lkclyou can take some of that for unit tests (new bugreport)20:37
ghostmansdlkcl, raised
ghostmansdI've estimated it with 500 for now, please adjust it as appropriate :-)21:40
ghostmansdI'm in the middle of implementing setvl test21:40
lkclprogrammerjake, toshywoshy meeting22:04
lkclcesar, ^22:04
klysa lingering query of mine, given that kazan can do trig and calculus, how many fpga bits would be devoted to internal lookup tables for the alu?22:32
programmerjakedepends on which algorithms we pick22:48
programmerjakea few kbits if we use goldschmidt division22:48
programmerjakeonly for div, not counting trig there22:48
Veera[m]<lkcl> "Veera, are you happy to help add..." <- Oh. Ok. Sorry for late response.; your leads!22:54
openpowerbot[slack] <github> signin22:54
programmerjakeVeera: if you want to work on that, I already figured out building it:
klyslkcl, what's the latest fpga dev board you're using and how many (?bits) does it have left for new stuff?23:09
Veera[m]programmerjake:  Nice. Let's wait for lkcl response23:10
programmerjakecurrently using the orangecrab and/or arty t100 iirc, they both have space for several megabits23:26
programmerjakeklys: ^23:27
klysoh okay thanks programmerjake23:29
klysi wonder which one is compatible with openocd23:31
programmerjakethe arty t10023:32
klysthx again23:32
programmerjakethe orangecrab should be compatible if you use an external jtag dongle, but it uses dfu through usb by default23:32
lkclVeera[m], i put everything into here
lkclyes i have a digilent arty a7-100t and it only takes about 35% of it *if* you cut the L1 I/D-Caches down to only 4 entries rather than 64 rows23:33
lkcli got some 1bitsquared 256mbit PMODs (2 of them) as well, which means it's bootable without needing DDR323:34
lkclklys, all of them are compatible with openocd23:35
lkclalthough the orangecrab is... well, you're better off using the associated tools23:36
lkclVeera[m] collected them all into an automated-install-script;a=blob;f=fpga-boot-load-prog-install;hb=HEAD23:36
klys101,440 logic cells on an arty t100.  how many occupied so far?23:37
lkclonly about 35%23:38
lkclbut that's only if you cut down the L1 cache to 4 rows rather than 64 rows23:38
klysand it has LUTs except those are different23:38
lkclit gets BIG, very quickly, because TLB virtual memory is a CAM, and FPGAs are horribly inefficient at doing CAMs23:39
lkclyes, it's a little complicated23:39
lkclthe usual way of judging "LUTs" is a LUT423:39
lkclthe a7 has LuT4s, LUT5s and LUT6s23:39
lkcland you can consequently fit a hell of a lot more into less LUT6s23:40
lkclso that "100k" number is "equivalent number if you did everything in LUT4s"23:40
lkclthere's actually only 60k LUT6 logic cells but it's *equivalent* to 100k LUT4 logic cells23:41
lkclsomething like that23:41
klysoh interesting, so there are parts that might expand to fit available space such as L1 cache23:42
lkclmore that there's a command-line option in soc for *reconfiguring* how large you want the L1 cache to be23:43
lkclthere's no "might" involved, because FPGA bitstreams don't do "might" :)23:43
klysif you are romming in a look up table, does that take LUTs too?23:43
lkclno, that ends up in SRAM (with no write signal)23:43
klysso thanks now I worry less23:44
klysI've been coding a simple nybble code interpreter in my spare time this week23:45

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