| kanzure | lkcl: missed that. | 00:04 |
|---|---|---|
| kanzure | oh nevermind. hi. | 00:04 |
| lkcl | kanzure: there's always next week. same time. UTC 22:00. i can add you to a calendar invite reminder? | 04:18 |
| lkcl | programmerjake, the openpower.util.log function has had a SILENCE_LOG environment variable for 8+ months | 04:19 |
| lkcl | i'm... how to put it delicately... "slightly raising an eyebrow" that you are only just learning of this, and sent a message to the list | 04:23 |
| lkcl | "there must be less print() statements", but didn't check the source code to find that there *aren't* any | 04:24 |
| lkcl | they've all been replaced with a call to log() | 04:24 |
| lkcl | the thing that's puzzling me somewhat is that i would have expected your first reaction to have been to look at the source code searching for evidence of print() statements | 04:25 |
| lkcl | because you would have found that there aren't any | 04:26 |
| programmerjake | well, I'm raising an eyebrow that you didn't check... openpower-isa.git: | 05:11 |
| programmerjake | `grep '^\W*print *(' -R . | wc -l` | 05:11 |
| programmerjake | 1080 | 05:11 |
| programmerjake | there are >3x as many print calls as log calls -- 301 log calls vs. 1080 print calls | 05:13 |
| programmerjake | as of commit 32b94e99b7e0f863a7f6c5eeb1d8c6dff38fcf31 Date: Tue Jun 14 15:13:43 2022 +0100 | 05:13 |
| programmerjake | in any case...gitlab-ci needs to have less output lines for it to be readily useful when a build fails | 05:15 |
| *** kylel1 is now known as kylel | 07:07 | |
| lkcl | programmerjake: then set SILENCELOG=1 as an environment variable | 12:06 |
| lkcl | 8+ months ago i focussed on those print() statements that helped lauri. | 12:15 |
| lkcl | that was focussed on pysvp64sim. i left everything else | 12:15 |
| ghostmansd[m] | Hi folks, a quick question: when does OPF meeting takes place? | 14:39 |
| ghostmansd[m] | And could someone PM me the credentials so that I'll be able to visit it? | 14:39 |
| octavius | ghostmansd[m], same link as yesterday, same time | 14:53 |
| ghostmansd[m] | Ah OK so these two meeting are once per two weeks? | 15:02 |
| ghostmansd[m] | I have some event in calendar sent by Luke, but it shows that meeting happens on Thursday... | 15:03 |
| octavius | ghostman[m], the tuesday meeting is once a week | 16:13 |
| octavius | the open power meeting is every two weeks | 16:14 |
| ghostmansd[m] | Ok, so OpenPower meeting is at Thursday, right? | 16:21 |
| octavius | third time lucky ghostmansd[m] :P | 16:40 |
| octavius | The OpenPower meeting is today (wednesday) | 16:40 |
| octavius | Actually wait, by the moscow timezone, yeah | 16:41 |
| octavius | I should have specified the timezone, sorry | 16:41 |
| octavius | Also, just checked my past emails, you're included on there, check that it's not in spam | 16:44 |
| octavius | lkcl, can you send out today's meeting email? | 16:44 |
| lkcl | octavius, yep on it | 16:49 |
| lkcl | ghostmansd[m], https://www.timeanddate.com/worldclock/meetingdetails.html?year=2022&month=6&day=15&hour=21&min=0&sec=0&p1=2413&p2=166&p3=57 | 16:57 |
| lkcl | ghostmansd[m], you're on GMT+3, the meeting's at GMT 21:00, therefore it's actually midnight local time for you (just like yesterday) but strictly speaking it's 00:00 *thursday* aka 24:00 *wednesday* | 17:04 |
| lkcl | 4 hours from now, basically :) | 17:04 |
| lkcl | Veera[m], are you happy to help add cvc5 to the yosys script? https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD | 17:06 |
| programmerjake | if you want to work on that, I already figured out building it: https://gitlab.com/programmerjake/nmigen/-/blob/smtlib2-expr-support/.gitlab-ci.yml | 17:14 |
| programmerjake | lkcl: i am planning on adding that myself later if no one else does that first | 17:15 |
| programmerjake | as part of changing our build scripts to work with smtlib2 nmigen | 17:16 |
| programmerjake | I'm currently blocked on: https://github.com/YosysHQ/sby/pull/170 | 17:17 |
| programmerjake | so am working on gitlab-ci server stuff meanwhile | 17:17 |
| ghostmansd[m] | Perfect folks, thanks for the link! I'll try joining today (or, well, on Thursday). | 17:18 |
| ghostmansd | https://libre-soc.org/irclog/%23libre-soc.2022-06-14.log.html#t2022-06-14T20:27:26 | 20:05 |
| ghostmansd | lkcl, since we're going to publish setvl, svstep, svshape and svremap, I had to rebase the branch so that these appear first | 20:05 |
| ghostmansd | but there're worse news, I think we should provide binutils tests for each of these | 20:06 |
| ghostmansd | I'll raise the task about it; these are not show-stoppers and can indeed be already published to review, as long as they have tests | 20:07 |
| ghostmansd | the latter conclusion is my assumption, since all commits from Alan I had a chance to look at, unsurprisingly come with tests | 20:08 |
| ghostmansd | lkcl, would it be OK if I raise task on these four, or you'd rather prefer to see one giant task about binutils tests? | 20:09 |
| ghostmansd | or, maybe, both? a giant task on binutils tests and subtask about these 4? | 20:09 |
| ghostmansd | FWIW, draft insns already have tests, since I intended to publish these from the very beginning :-) | 20:10 |
| lkcl | ghostmansd, yes good call on tests. | 20:35 |
| lkcl | hmmm we're at EUR 3275 on 577 https://bugs.libre-soc.org/show_bug.cgi?id=577 | 20:36 |
| lkcl | you can take some of that for unit tests (new bugreport) | 20:37 |
| ghostmansd | lkcl, raised https://bugs.libre-soc.org/show_bug.cgi?id=857 | 21:36 |
| ghostmansd | I've estimated it with 500 for now, please adjust it as appropriate :-) | 21:40 |
| ghostmansd | I'm in the middle of implementing setvl test | 21:40 |
| programmerjake | https://spectrum.ieee.org/plastic-microprocessor | 21:41 |
| lkcl | wooow | 21:52 |
| lkcl | programmerjake, toshywoshy meeting | 22:04 |
| lkcl | cesar, ^ | 22:04 |
| klys | a lingering query of mine, given that kazan can do trig and calculus, how many fpga bits would be devoted to internal lookup tables for the alu? | 22:32 |
| programmerjake | TBD | 22:47 |
| programmerjake | depends on which algorithms we pick | 22:48 |
| programmerjake | a few kbits if we use goldschmidt division | 22:48 |
| programmerjake | only for div, not counting trig there | 22:48 |
| Veera[m] | <lkcl> "Veera, are you happy to help add..." <- Oh. Ok. Sorry for late response. https://github.com/cvc5/cvc5; your leads! | 22:54 |
| openpowerbot | [slack] <github> signin | 22:54 |
| programmerjake | Veera: if you want to work on that, I already figured out building it: https://gitlab.com/programmerjake/nmigen/-/blob/smtlib2-expr-support/.gitlab-ci.yml | 23:05 |
| klys | lkcl, what's the latest fpga dev board you're using and how many (?bits) does it have left for new stuff? | 23:09 |
| Veera[m] | programmerjake: Nice. Let's wait for lkcl response | 23:10 |
| programmerjake | currently using the orangecrab and/or arty t100 iirc, they both have space for several megabits | 23:26 |
| programmerjake | klys: ^ | 23:27 |
| klys | oh okay thanks programmerjake | 23:29 |
| klys | i wonder which one is compatible with openocd | 23:31 |
| programmerjake | the arty t100 | 23:32 |
| klys | thx again | 23:32 |
| programmerjake | the orangecrab should be compatible if you use an external jtag dongle, but it uses dfu through usb by default | 23:32 |
| lkcl | Veera[m], i put everything into here https://bugs.libre-soc.org/show_bug.cgi?id=835#c0 | 23:32 |
| lkcl | yes i have a digilent arty a7-100t and it only takes about 35% of it *if* you cut the L1 I/D-Caches down to only 4 entries rather than 64 rows | 23:33 |
| lkcl | i got some 1bitsquared 256mbit PMODs (2 of them) as well, which means it's bootable without needing DDR3 | 23:34 |
| lkcl | https://libre-soc.org/HDL_workflow/HyperRAM/ | 23:34 |
| lkcl | klys, all of them are compatible with openocd | 23:35 |
| lkcl | although the orangecrab is... well, you're better off using the associated tools | 23:36 |
| lkcl | Veera[m] collected them all into an automated-install-script https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=fpga-boot-load-prog-install;hb=HEAD | 23:36 |
| klys | 101,440 logic cells on an arty t100. how many occupied so far? | 23:37 |
| lkcl | only about 35% | 23:38 |
| lkcl | but that's only if you cut down the L1 cache to 4 rows rather than 64 rows | 23:38 |
| klys | and it has LUTs except those are different | 23:38 |
| lkcl | it gets BIG, very quickly, because TLB virtual memory is a CAM, and FPGAs are horribly inefficient at doing CAMs | 23:39 |
| lkcl | yes, it's a little complicated | 23:39 |
| lkcl | the usual way of judging "LUTs" is a LUT4 | 23:39 |
| lkcl | but | 23:39 |
| lkcl | the a7 has LuT4s, LUT5s and LUT6s | 23:39 |
| lkcl | and you can consequently fit a hell of a lot more into less LUT6s | 23:40 |
| lkcl | so that "100k" number is "equivalent number if you did everything in LUT4s" | 23:40 |
| lkcl | there's actually only 60k LUT6 logic cells but it's *equivalent* to 100k LUT4 logic cells | 23:41 |
| lkcl | something like that | 23:41 |
| klys | oh interesting, so there are parts that might expand to fit available space such as L1 cache | 23:42 |
| lkcl | more that there's a command-line option in soc for *reconfiguring* how large you want the L1 cache to be | 23:43 |
| lkcl | there's no "might" involved, because FPGA bitstreams don't do "might" :) | 23:43 |
| klys | if you are romming in a look up table, does that take LUTs too? | 23:43 |
| lkcl | no, that ends up in SRAM (with no write signal) | 23:43 |
| klys | so thanks now I worry less | 23:44 |
| klys | I've been coding a simple nybble code interpreter in my spare time this week | 23:45 |
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