Thursday, 2022-06-16

*** Ultrasauce is now known as sauce02:54
Veera[m]programmerjake: shall I update the script hdl-tools-yosys with support for cvc5 and smtlib2. Whether new bug to be opened or to report it in #835. Also yosys-0.13 is to be used with them or your provided link page versions (CI) to be used.03:15
programmerjakethe versions to use for now are the ones in the gitlab-ci file in the build_on_yosys_smtlib2-expr-support-on-0.13 section -- do note that the sby commit there is missing some other stuff needed, it works for ci but will probably not work for other libre-soc projects. I'm waiting on the sby PR to be merged03:18
programmerjakeso, imho it would be best to wait for that sby PR to be merged since then we can actually use sby master rather than having to make our own fork that merges both the stuff from that PR that hasn't yet been merged and from a different independent PR that already was merged.03:20
programmerjakePR to wait for:
programmerjakeother PR:
programmerjakeactually, now that I look at it, maybe it wasn't that one, but another PR...icr. i remember I was waiting on something though rather than just using the commit in #17003:21
programmerjakesince the commits in #170 don't include something that was already merged in sby master that iirc we need.03:22
programmerjakeso, sorry, but I think we should just wait03:23
programmerjakesorry for wasting your time03:27
lkclprogrammerjake, can i suggest to keep track of the PRs in the bugreport?08:43
lkclbut, also, if that takes too long we have to bear in mind that there's only 3 months left08:43
lkclyou cannot wait 2-3 weeks for a team outside of our control to react08:43
lkclif we have to make a temporary fork of sby then we make a temporary fork of sby08:44
programmerjakeI added it to the top comment.08:45
programmerjakewe can just create a task for writing everything, and move all the funding to that one, that way getting paid doesn't need to wait on the PR08:46
programmerjakeI'll keep waiting a bit tho08:46
lkclyep good idea08:47
programmerjakeif they haven't merged the PR by next week, we can think about making our own temporary sby fork then08:47
lkcli've just created a repo anyway, which will help solve the stability issue08:48
lkcldang the moving targets are creating a mess08:48
lkclshould have caught that a long time ago and used a git tag for everything08:48
programmerjakeI'm brain-dead, icr what stability issue you mean08:48
lkcl:) dev-env-setup scripts breaking08:49
programmerjakeimho if you change it to a tag or commit hash, using the upstream repo should still be fine...we can reasonably expect they won't move tags or delete commits08:50
lkclwhich one's the yosys git repo needed?;a=summary08:50
programmerjakethe git branch I'm using for yosys 0.13 is smtlib2-expr-support-on-0.1308:52
programmerjakeeverything I submitted was merged upstream, so when we move off 0.13 it should all be there08:53
programmerjakefor yosys at least08:53
lkclnot yosys-0.13-with-write_jny08:53
programmerjakeyosys-0.13-with-write_jny is the tag for the 0.13 branch with stuff cherrypicked from upstream...before I added any of the smtlib2 stuff08:54
programmerjakebasically I cherrypicked all the commits I needed to get nmigen tests to pass08:55
lkclahh ok08:55
programmerjakemostly just write_jny, but there are a few misc commits too08:55
lkclfrickin lot of work, sigh08:55
lkclok i'm re-running hdl-tools-yosys to make sure it's all good08:56
lkclthere's an msc student from the openpower academic group who's been very kindly tasked with checking that ls180 can be synthesised to GDS-II files with Cadence VLSI tools08:57
programmerjakewell...speaking of a lot of work, i'm working on adding unsubscribe links to the build emails...discovered ssh-keygen can be used for signing and verifying files, so I'm using that for url signatures since it's likely to be done correctly and it's waay easier to use than installing openssl 3.0 so I can use and verify hmacs08:57
programmerjakewhat fun!!! about as much fun as breaking your arm08:58
lkclit's USD 90 million worth of tools they've access to08:58
programmerjakeit's interesting and useful but sounds like a total pain to get working08:59
lkcland it's also highly significant: we'd be able to say that ls180 is synthesisable on much lower geometries than 180nm08:59
programmerjakethat depends on if they're using much lower geometries or not...08:59
lkclwell, they've experience in dealing with that08:59
lkclthe tools don't care what you end up using09:00
lkclthey have access to the PDKs, they can run the synthesis and the DRC at those lower geometries09:00
lkclwithout actually submitting to a Foundry09:00
lkclthe absolutely crucial bit of information for us is, "did it pass DRC"09:00
lkcli'm going to ask Veera to add cvc5 to hdl-tools-yosys anyway. hmm under a separate bugreport.09:02
programmerjakeok, I'd recommend using the build instructions in the gitlab-ci file...iirc cvc5 needs java to build09:02
lkclurrr fer f***'s sake. sigh09:03
lkclno don't answer that lol09:03
programmerjakethey use it for their parser generator09:03
lkclohh antlr most likely09:03
programmerjakeyeah, antlr309:03
lkclit's quite popular.09:04
programmerjakeI've used it before, it's relatively nice09:04
lkclthere's a debian package for antlr3.09:05
programmerjakethough I ended up switching to a packrat parser generator I wrote for some stuff, and just writing custom recursive-descent parsers for the rest09:05
programmerjakeI tried installing the debian package, it ignores it09:05
lkclnggh they need antlr3.409:05
lkclyyep, debian has antlr3.2 sigh09:05
lkclah well09:06
* lkcl need to get up and go walk round the garden09:06
programmerjakeeclipse integration for that parser generator I wrote:
programmerjakeexample grammar:
lkcloo bnf-like grammar, ooo09:10
programmerjakeit actually uses something that imho is better than bnf:
lkclit reminds me of yacc/bison09:11
lkclordered choices. interesting09:12
programmerjakethe idea is it's never ambiguous09:12
lkcli'm supposed to be afk in the garden! :)09:12
programmerjakewell, I'm done for the day, gn09:54
lkclnight jacob09:55
lkclcesar, i just emailed you about some RFPs for you. there are three, they each need their own separate email and separate subject-line!13:20
lkclbecause they are three separate NLnet projects.13:20
cesarAmazing, thanks! I'll get to it, and send you the drafts.13:28
openpowerbot[mattermost] <lkcl> magic. it's almost EUR 5,000 for you - you did most of the work on TestIssuer's SV FSM so i found a budget for that13:29
octaviusApologies for being quiet, been studying and writing. Currently I'm comparing the SIMD and vector topologies.15:27
octaviusFrom my current understanding, a vector architecture is sort of like a block of memory where VL determines how much of this memory the instruction will use, right?15:27
octaviusWhereas SIMD has predefined register lengths, and thus you will need to regularly move data to/from main memory (or cache) if you code has more elements than a SIMD register can store.15:27
octavius*your code15:27
lkcl"block of memory" --> "block of register elements"... but yes15:30
octaviusAh ok15:31
lkclVectors -> variable-length blocks of register elements15:31
lkclSIMD -> fixed-length blocks of register elements15:32
lkclthe problem with SIMD should be pretty damn obvious, if the SIMD fixed width is 16 elements, then how are you going to process only 15 elements? or 17?15:33
lkclSIMD ISAs "solve" that as follows:15:33
lkcl* add an extra SIMD instruction to do 8 elements15:34
lkcl* add another to do 415:34
lkcl* add another to do 215:34
lkclthen you do a binary-calculation with branches, subtracting the number that you've covered, 8+4+2+115:34
lkcland that way in a pre-preparation step with an *identical copy* of the entire inner loop of the algorithm, you15:35
lkcl[optionally] do 8 elements15:35
lkcl[optionally] do 4 elements15:35
lkcl[optionally] do 2 elements15:35
lkcl[optionally] do 1 element15:35
lkclohhh nooow we have rounded up to 16 elements,15:35
lkclnoooow we can do the 16-way SIMD inner loop15:36
lkcl(we're up to FIVE copies of the entire inner loop algorithm so far...)15:36
lkclwhen i said last night that that sigarch "simd considered harmful" article massively understated things, it was because they deliberately only chose AVX-215:37
lkcl(and for MIPS, only the 2-wide SIMD)15:37
lkclif they'd attempted to demonstrate with AVX-256 they'd have literally had to have written assembler code longer than the entire article15:38
lkclbottom line is, it's kinda astounding that nobody has noticed how bad SIMD really is15:38
lkclthey just "put up with it" in a resigned fashion15:38
octaviusThat's insane :'(15:57
octaviusSo ifSo if for example I'm to add two vectors of length 15, vec(A) + vec(B).16:07
octaviusSIMD has to generate 8-element SIMD, then 4-element, then 2, then 1.16:07
octaviusThen the results are written into memory? Surely you don't need to do any more computation than that?16:07
programmerjakelkcl: please check
lkclprogrammerjake, ack16:13
programmerjakethis too:
lkclresponding, 1 sec, in the middle of something16:19
octaviusI need to go, will be back in a few hours, no rush16:20
ghostmansdfolks could you remind me a command to launch all tests for openpower-isa?16:27
ghostmansdI'm changing svp64py again, and don't want to break it like previously16:27
lkclghostmansd, lol16:31
lkclmmm.... 1 sec...16:31
lkclany of those starting "test_caller_svp64" should do it16:32
lkclghostmansd, btw, you might have noticed, the entire meeting yesterday went completely off-agenda, but in a good way16:45
lkcli found it funny, i explained to you privately how i was expecting it to go, blah blah, and we got thrown a curve-ball on limited time :)16:47
ghostmansdyeah I was also somewhat surprised, since I even should've taken part in agenda dedicated to binutils works :-)17:03
ghostmansdstill it was a nice discussion17:03
ghostmansdOK I'll check test_caller_svp64 tests17:04
lkclghostmansd, oh fer god's sake :)
lkclya put a EUR 50 cents into a bugreport :)18:01
lkcltoo late now because you've put in the RFP: do try to round things up to at least EUR 5 preferably 10 :)18:01
lkclVeera[m], i added those 2 extra images, they're quite simple
ghostmansdlkcl, by the way I even had to ask here how to do it lol :-D18:33
ghostmansdand programmerjake explained that I had to do it a string!18:34
ghostmansdI don't remember why it was this way, perhaps I understood this 15 percent way too literally18:35
ghostmansdAhem... Would it be way too much if the objdump "etalon" to be compared in test takes 2400+ lines?... Same for the assembler listing which is used as an input before being fed into binutils.18:38
ghostmansdI guess binutils maintainers would beat the crap out of me. Also, on second thought, there's no need for this comparison to take place, eh?18:39
programmerjakeah, because python floats don't represent decimals exactly, so you need a string so the toml parser doesn't use a python float...cuz money needs to have exact arithmetic18:40
ghostmansdWhat'd be the canonical way to check each of these only once? I mean, I don't really bother how the insn would look like. I simply wanted to check some corner cases but keep assembly listing (and the corresponding dump) minimalistic.18:41
ghostmansdI think there must be something in itertools...18:41
ghostmansdI mean, this is OK to commit, it covers many cases well. But hell, post it on mailing list...18:43
ghostmansdWhoa 10420 lines for svremap... Way too long.19:32
ghostmansd[m]Ok, all done, but, as I mentioned, patches will be way too large. Any ideas?20:18
ghostmansd[m]On the other hand, this checks operands together, so perhaps this is good thing after all.20:25
octaviusWhat does the "P64" in SVP64 mean?22:22
octaviusI guess SVP64 is the same as SV (Simple Vectorisation)?22:22
programmerjakeprefix 64-bit because the prefixed instructions are 64-bit in size22:25
programmerjakethe idea is there may be a different instruction format and the P64 is needed to differentiate them...originally we were planning on having 16-bit instructions where the sv data was specified as part of a separate instruction that set the sv data for the next few instructions...that has stalled/been dropped22:28
programmerjakeback when we were using risc-v instead of openpower, the format was called svp48 because it was a 16-bit prefix on a 32-bit instruction, giving a 48-bit instruction22:30
octaviusAh ok, thanks Jacob!22:52

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