Thursday, 2022-06-23

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lkclmelted-brain :)09:47
lkclno there isn't09:47
lkclit's a csv file09:47
programmerjakeimho it would be useful to switch to json5 format, rather than csv10:00
programmerjakehttps://packages.debian.org/source/bullseye/python-json510:00
programmerjakejson5 is json with comments and a few other things to make it easier for humans to use10:01
programmerjakeor we could use toml10:01
programmerjakejson and toml both are widely supported10:02
programmerjakehttps://github.com/toml-lang/toml/wiki#implementations10:03
programmerjakeby contrast with yaml -- yet another maximal language (not really what yaml means, but i find it amusing)10:05
lkclprogrammerjake, yyeah, apart from anything it would solve the issue of line-wrap10:29
lkclbut then again also make it slighly harder to extract / compare against microwatt10:30
programmerjakejq to the rescue!!10:30
lkcland, drat, introduce massive extraneous crap due to repetition of the key-value pairs10:30
lkclunless the rows stayed as lists10:31
programmerjakethat can be done...10:31
* lkcl trying to recall what went into the parser, it's not just plain "read the csv"10:31
* lkcl not feeling it to be a high-priority item, more along the lines of "if it ain't broke don't fix it"10:32
programmerjakeyeah, though imho it would be useful to at least have comments in your csv...just check if the first col starts with `#`, if so, ignore the whole row. simple10:33
lkcland with 15 weeks to the october deadline (12 if excluding "NLnet putting in last minute EU Grant transfer requests") i'm inclined to suggest leaving anything that takes a long time10:34
lkclyyeah that might work, 1 sec let me see...10:34
programmerjakeimho switching to json would take <1 day, probably 1-2hr10:34
lkclhttps://stackoverflow.com/questions/14158868/python-skip-comment-lines-marked-with-in-csv-dictreader10:34
lkclpffh10:34
lkclprogrammerjake, no it damn well would not10:34
lkclthat's a 1-line addition, and get_csv is a single function, i know (appx) where it is10:35
programmerjakewhy not? doesn't everything that reads those csvs go through the decoder classes? we could switch it there and it would be pretty simple to do.10:36
programmerjakenote we don't want pure json -- no comments10:36
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=86f0c748efb10c84e014583cc400dee29564f7a710:40
lkclthat's brain-dead-easy.10:40
programmerjakeimho it'd be useful to support blank lines and comments with spaces before the #10:41
programmerjakewith that code a blank line will cause row[0] to raise an error10:41
lkclthat's good: that will stop people putting in blank lines and comments with spaces before the #10:42
lkclit's enough10:42
programmerjakek10:42
programmerjakenow we have comments -- add license info to the csvs!10:43
lkcltoo much else to do, and it means octavius (and anyone else) can at least comment out in-development...10:43
lkcloh yeah :)10:43
programmerjake:)10:43
lkclwhich... has to be CC-4 because it was taken directly from IBM-licensed microwatt source code10:44
lkclalthough there's a case for there not *being* a license because it's "specification"...10:44
programmerjakeat least we could add attribution, even if it isn't a copyright license10:45
programmerjakealso, a lot of that is derived from the openpower spec, not just microwatt10:46
programmerjakeiirc10:46
programmerjakein any case, gn10:46
lkclnight :)10:47
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lkclmoornin octavius. i noticed you melted your brain?13:26
lkclwhilst i have been doing totally-messed-up work patterns for 30 years it has... consequences i cannot recommend :)13:26
lkcli added a 1-line fix so you can do "# comment" in csv files btw13:26
lkcli'd already done the pseudo-code for bmask because it's a little quirky13:27
lkclhttps://libre-soc.org/openpower/sv/vector_ops/discussion/13:27
lkclsuch as, "if RB is zero then don't load it from the regfile, use the mask value of all 1s"13:27
lkclif _RB = 0 then mask <- [1] * XLEN else mask = (RB)13:27
lkcland the other thing to remember is, objects in the pseudocode are SelectableInt()s13:28
lkcland consequently have an indexing operator13:28
lkclmask[0:1] gets you bits 0..113:28
lkclthat's *NOT* the same as python range!13:29
octaviusHi lkcl, thanks!13:31
lkclyou shouuuld be able to just throw that into av.mdwn but i haven't syntax-checked it.13:38
octaviusPutting into av.mdwn I get an IndexError: pop from empty list when running PyWriter15:03
lkcloctavius, that's a pain. use binary-search to cut out lines until it passes15:28
lkclthen put back half of them, etc.15:29
lkclnarrow it down to one line15:29
lkcloctavius, if you get really stuck, chuck it in a branch and i'll take a look15:43
octaviusLooks like it's not the pseudo code15:49
octaviuswould not having a definition in svp64.py cause this? I currently have the b-form part commented out15:49
ghostmansdthe most exhaustive documentation ever: https://libre-soc.org/openpower/sv/svstep/15:54
ghostmansd:-)15:54
ghostmansdahem... should I add this link to commit?15:54
ghostmansdhttps://libre-soc.org/openpower/isa/simplev/ I'll add this15:55
octaviuslkcl, I added the bmask op (but PyWriter is not working, and the bitfields in svp64.py are probably wrong)15:56
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lkclghostmansd, i know :)17:05
lkcloctavius, you missed "Special Registers Altered" None17:06
octaviusXD17:11
lkclhmmm what the heck's going on... BM2-Form not recognised... hmm...17:13
octaviusyeah17:13
lkclah ha. power_enums.py17:13
lkclok all good17:13
lkclthat was more hassle than it should have been17:14
lkclghostmansd, ahhh... actually.... svstep is ahhh not supposed to be added17:18
lkclhttps://libre-soc.org/openpower/isa/simplev/17:18
ghostmansdeeeeh... how comes?17:19
lkclnotice the pseudocode?17:19
lkclfor setvl?17:19
ghostmansdyep, why can't it be svstep insn?17:19
lkclit's a waste of encoding space17:20
lkclsetvl with vf=1, ms=0, vs=0 does the exact same job17:20
ghostmansdOK, let's approach from another angle. It's present in parts of doc, it's present in svp64, it's present even in task I've been doing for quite a long time (and in fact still do, rebasing).17:20
lkcli know17:20
ghostmansdsigh17:21
ghostmansdThis patchset really experiences my patience... :-)17:21
lkcluh-huhn...17:21
ghostmansdOK I'll drop it.17:21
lkcli wondered why the hell i hadn't documented the page17:22
lkclwelcome to developing a spec at the same time as implementing it17:22
lkcli thought i'd got all these things sorted out before saying "ok go" on binutils, sorry17:23
ghostmansdhuh :-)17:23
ghostmansdOK don't worry, that's OK17:23
ghostmansdat least it's good we found it now, before it's in upstream17:23
ghostmansdthe latter would also not be an extreme issue, though17:23
ghostmansdbut still is better to find it now17:24
ghostmansdkinda pissed that I just implemented tests for it about 20 minutes ago17:24
ghostmansdbut OK :-)17:24
lkcli'm even finding unit tests for it!17:24
lkcli'm going to have to look at that reeaaally carefully17:26
ghostmansd> i'm even finding unit tests for it!17:27
lkclthere's only one17:27
ghostmansdwell you could've even found it in binutils lol17:27
ghostmansdso, svstep is dropped entirely, right?17:28
ghostmansdI'll drop it from pysvp64asm and patches I'm going to submit17:28
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_setvl.py;h=fe8ffd987c4a120654047942d335bb8e081b0514;hb=a7f3fa7ab2c87d75d0c562eb12d73e01d19095f1#l32717:29
lkcli don't know yet.17:29
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lkclnnope, it has to stay17:33
lkcli know what's going on17:33
lkclit has to stay17:33
lkcli was in the middle of something for DCT/FFT Modes, and hadn't documented it.17:33
lkclsorry about that: it's a necessary instruction. i'll carry on documenting it17:34
ghostmansdfuck Luke I just dropped it17:36
ghostmansdOK I hope it's in reflog17:36
lkclas long as you've not done "git gc" then yes17:39
lkclthere's so many aspects to this, it's mental. i'm annoyed with myself for not documenting the additions to svstep when i made them (about 7 months ago)17:52
programmerjakeeven if you do git gc, iirc by default reflog entries don't expire for 30d17:58
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tplatenafter changing the DQS/data pins for the OrangeCrab as in the merge request from today, I get: Warning: Failed to find a route for arc 2 of net ddrphy_ddr3_0__a__o_fclk.18:56
tplatenERROR: Routing design failed. Most likely some of the pins is still wrong, I'll do a comparision with the schematics18:57
programmerjakei'll note it appears you put one half of each diff pair with the other diff pair...does the ecp5 even support that? i'd expect the ecp5 has each diff pair only work on the exact 2 pins lattice specifies, not allowing you to mix and match them19:11
programmerjakethough i could be mis-interpreting the pin assignments in nmigen-boards19:12
programmerjaketplaten: ^19:12
programmerjakee.g. if a,b and c,d are two diff pairs, it appears you tried to use diff pairs a,c and b,d19:13
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cesarOn nmigen, DiffPairs("a,c", "b,d") means a,b is one pair, c,d is the other.19:51
cesarThe first list are all the positives, the second list is all the negatives.19:52
cesar... respectively.19:53
tplatenI interpreted the schematics wrong, and I'm not the only person who did that.20:06
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ghostmansdlkcl, I've updated the patches, let's see whether there're more iterations needed20:46
ghostmansdI must admit it took a long time, since I also re-visited the code and found an option to keep it even shorter. I hope they won't object to the fact I added a new operand flag. This is for operands which take form 1..n instead of 0..n-1 (we have this logic for SVxd, SVxy, SVxz and SVi).20:51
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lkclghostmansd, awesome23:38
lkclnew op flag is a good idea i feel, it makes things clear what's going on23:38
lkclif there's a future revision, the actual spec pages start at https://libre-soc.org/openpower/sv23:41
lkclnot https://libre-soc.org which is the general wiki/website for the entire project23:41

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