| lkcl | it's in-yer-face and factual. i can't think of a way to soften the blow of plain facts, not when put into a non-socially-contextual document like this | 00:08 |
|---|---|---|
| lkcl | if it was a "chat system" or "an email list" i could put, "there's no easy way to say this, you just have to take a deep breath, but...." | 00:08 |
| lkcl | such phrasing is completely inappropriate for this type of document. | 00:09 |
| octavius | Of course, it's difficult to refute the facts | 00:10 |
| octavius | And given it's in the spec, not the primer, it's more acceptable | 00:10 |
| tplaten | Yesterday I install iverilog, now I have a look how to run simulations using iverilog, with the recent changes to gram | 12:12 |
| lkcl | tplaten, it's quite simple, just run the script. | 13:59 |
| lkcl | caveat: you need to obtain the ECP5 verilog model files. | 13:59 |
| lkcl | they're proprietary, sigh | 13:59 |
| lkcl | octavius, i created this https://libre-soc.org/openpower/sv/executive_summary/ | 14:00 |
| lkcl | i'm also updating https://libre-soc.org/docs/pypowersim/ because i want to link to it in the summary | 14:02 |
| tplaten | I'll have look now, I have been afk for several hours | 14:09 |
| octavius | hi lkcl, yeah I saw, just reading now. good idea | 14:14 |
| tplaten | I guess the file that I have to feed into iverilog is build/top.debug.v | 14:25 |
| tplaten | Yes, iverilog reads my generated files | 14:27 |
| tplaten | *** These modules were missing: | 14:27 |
| tplaten | BB referenced 18 times. | 14:27 |
| tplaten | CLKDIVF referenced 1 times. | 14:27 |
| tplaten | DDRDLLA referenced 1 times. | 14:27 |
| tplaten | DELAYG referenced 16 times. | 14:27 |
| tplaten | DQSBUFM referenced 2 times. | 14:27 |
| tplaten | ECLKBRIDGECS referenced 1 times. | 14:27 |
| tplaten | ECLKSYNCB referenced 1 times. | 14:27 |
| tplaten | EHXPLLL referenced 1 times. | 14:27 |
| tplaten | FD1S3AX referenced 2 times. | 14:27 |
| tplaten | IB referenced 3 times. | 14:27 |
| tplaten | IDDRX2DQA referenced 16 times. | 14:27 |
| tplaten | OB referenced 33 times. | 14:27 |
| tplaten | ODDRX2DQA referenced 18 times. | 14:27 |
| lkcl | tplaten, https://libre-soc.org/irclog/%23libre-soc.2022-07-23.log.html#t2022-07-23T13:59:35 | 14:35 |
| lkcl | "<lkcl> caveat: you need to obtain the ECP5 verilog model files" | 14:36 |
| lkcl | tplaten: ^^^^^^^^^^^^^^^^ | 14:36 |
| lkcl | https://git.libre-soc.org/?p=gram.git;a=blob;f=gram/simulation/README.md;hb=HEAD | 14:37 |
| lkcl | line 8 | 14:37 |
| lkcl | i cannot give you copies of those files because they are proprietary. | 14:38 |
| tplaten | I saw ECP5 instances models from a Lattice Diamond installation | 14:40 |
| tplaten | the same thing as with an old Xilinx FPGA, I had to install the non-free toolchain | 14:41 |
| lkcl | tplaten, give me 1 second i am setting you up with ssh access to tplaten@talos1.libre-soc.org using your gitolite3 ssh key | 14:41 |
| lkcl | please check it now - *do not* attempt to type a password | 14:42 |
| lkcl | ssh -v -p922 tplaten@talos1.libre-soc.org | 14:42 |
| tplaten | it works | 14:44 |
| tplaten | ECDSA key fingerprint is SHA256:JvNPmJpOKbiSHT1W3LcweZYBiZfkPT/t+k4niJNklec. | 14:44 |
| lkcl | excellent | 14:44 |
| lkcl | i leave it to you to explore the home directory and the rest of that system. | 14:45 |
| tplaten | I see there is ecp5u.tgz | 15:04 |
| cesar | lkcl and tplaten : I have, locally, a couple of fixes needed for successfully running the Icarus simulation in Gram. Could you please grant me write access the Gram git repository? | 15:13 |
| tplaten | I cannot do this, so it is up to lkcl | 15:13 |
| cesar | Sorry, I meant to say "lkcl , could you please grant me access..." | 15:15 |
| cesar | I also backported ecp5_crg.py from ls2.git to gram, which is needed for successfully generating the headless example. Also created a headless-orangecrab.py (untested). | 15:26 |
| cesar | tplaten: You can place the ECP5 model files in gram/simulation/ecp5u, where gram/simulation/rumsimsoc2.sh expects them. | 15:33 |
| cesar | (I propose merging runsimsoc2.sh into runsimsoc.sh, the only difference is the location of the ECP5 model files) | 15:39 |
| lkcl | cesar, sure | 15:47 |
| lkcl | cesar, tplaten, i've added you both | 15:47 |
| cesar | Cool, thanks. | 15:47 |
| tplaten | Guess I have first to convert the top.il to verilog using yosys before I can use it with iverilog. | 15:50 |
| cesar | tplaten: The runsimsoc.sh script takes care of that. | 15:59 |
| tplaten | I'll be afk for about half an hour again, then I'll be back the rest of the evening | 16:00 |
| cesar | tplaten: Please do a git pull on gram.git. Running ./runsimsoc.sh in gram/simulation should run, and pass all tests. | 18:34 |
| tplaten | I did | 18:35 |
| cesar | Cool. I'll clean and push my changes to the headless examples, later. | 18:44 |
| tplaten | It works: http://platen-software.de/tobias/libre-soc/simsoc.txt | 18:57 |
| lkcl | fantastic | 19:42 |
| tplaten | Nearly ten years since I started learning python. And libre-soc is not the only project that uses python where I am active in. | 19:46 |
| lkcl | 1/3 of the world's programmers use python, now. | 19:48 |
| tplaten | I recently started learning GDScript which is similar to Python. That should be easy to learn in a short amount of time. And the glue code for libsurvive is written on python too. It took me only a few weeks to learn python. | 19:51 |
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