Wednesday, 2022-07-27

octaviussystemd-free distro supporting PII :)00:01
lkclprogrammerjake, ah nice, good catch02:01
lkcloctavius, that's a really good find, the anti-X distro.  they're clearly "anti" systemd but are funny about it11:49
lkclwhereas devuan is clearly "outrage outrage outrage outrage, anti anti anti anti"11:50
markosfmvis should be done now, and just finished with fishmv as well, will commit in a sec12:00
markoslkcl, please check12:01
markosprogrammerjake, you too please, I think I understood now what you were saying, I kept forgetting that default fp representation on power is FP6412:02
markoslkcl, just saw the comment about minor_22.csv for fmvis12:05
markoscould you please explain again why OUT should be set to NONE?12:06
markosnow it's IN1=NONE, OUT=FRS and it seems to work, perhaps you meant that in the comment?12:07
lkclmarkos, willdo12:11
lkclin fmvis? because RS is not read, it's produced.12:12
lkclin fmvis, all the bits of RS not set to the immediate are set to zero12:12
lkclin fishmv, you have to *add* 16 bits of immediate into the *existing* value of RS.12:13
lkclmarkos, yes i botched up on minor_22.csv, realised i'd made a mistake and reverted it.12:13
lkclyou got it right12:13
lkcl-    d0 = (imm >> 6) # MSBs 6-1512:14
lkcl+    d0 = (imm >> 5) # MSBs 6-1512:15
lkcli thought it might be something like that12:15
lkclhang on though...12:15
lkcl 426     d0,d1,d2 (16:25,11:15,31)12:15
lkcld0 is 25-16+1 = 10 bits long12:16
lkcld1 is 15-11+1 = 5 bits long12:16
lkcld2 is 31-31+1 = 1 bit long12:16
lkcl 345     d2 = (imm & 1) # LSB (0)12:18
lkcl 346     d1 = (imm >> 1) & 0b11111 # bits 1-512:18
lkcl 347     d0 = (imm >> 5) # MSBs 6-1512:18
lkclso that really doesn't look right / add up12:18
markosindeed, the missing bit is the sign13:35
markosjust checked and it doesn't get copied13:35
markosalmost fixed, you are right, it needed >> 614:03
markosthere, that should really fix it14:18
markosnegative numbers work now too14:19
markoslkcl, commit 04f20aa14:20
cesartplaten: I agree that there is a lot of duplication within gram and ls2. I guess, after we are satisfied that it really works, we can look into merging and refactoring. On LiteX, it's all centralized in litex-boards, maybe we can move common code into nmigen-boards.14:45
cesarThe CRG in ls2 seems more evolved and generic, but I suspect it's a work in progress.14:45
cesarThe simulation in ls2 seems to be more complete, including memory training. But it also includes a full simulated CPU, which is a bit overkill, I think,  when we only want to test the controller, at first. For that, the headless simulation is better, it's just a Wishbone bridge wired to a Verilog testbench.14:51
cesar(I am thinking into converting it into a cocotb testbench, maybe)14:54
lkclmarkos, hooray, that was a bitch of a job spotting the 27..30 instead of 26..3014:56
lkcli even managed to get +/- inverted for about 10-15 minutes14:57
lkclso anyway, i'm happy with that, congratulations, EUR 2,000 is yours.14:59
ckiehey, looking around the wiki but i can't tell what the state of the cpu part of the SoC is. i'm looking for a libre rpi equivalent16:04
octaviushi ckie, libre-soc can be run on an fpga, however something like an rpi (with an asic) is little away16:06
octaviuscurrently the orange-crab and a few other fpga boards have been tested with the libre-soc core16:06
ckieis it perhaps equivalent to the first rpi?16:06
octaviusActually hard to say16:07
octaviusI haven't ran it on an fpga myself16:07
ckiewhat can it do then?16:09
octaviusExecute binaries (compatible with Microwatt PowerISA cpu), Tim at Raptor Computing was able to run a web server on it recently16:11
octaviusAlso I seem to remember there being a maze game running on it as well16:13
ckiei guess i'll check in in a few years again then :p16:15
octaviusyw ckie :)16:16
lkclckie, it should now run joel shenki's microwatt linux-5.7 now that tim helped triage running ZephyrOS18:32
ghostmansd[m]lkcl, are the recent insn additions complete, or should I wait for some changes and updates?19:42
ghostmansd[m]I'm asking since if these are not ready yet, I can postpone adding them to binutils19:42
ghostmansd[m]So this is rather a question "are these stabilized?"19:43
ghostmansd[m]FWIW, I started working on disasm19:47
markosprogrammerjake, is there a difference between DOUBLE2SINGLE() vs plain SINGLE() helper function? in the beginning I had the former but was getting wrong results, hence the change, but I guess the bug wasn't in the pseudocode, but the wrong indices in's methods20:38
markosthanks for the fix in any case, however I have to say I would appreciate it more if you would point me to the problem as that would give me more reason to investigate and learn from it20:40
markosI don't mind others fixing my bugs though, far from it :)20:42
programmerjakeSINGLE() is the function used when the input is known to be a f32 in a f64, it doesn't round or anything, so it's a lot cheaper to implement in hardware. DOUBLE2SINGLE iirc does a round-to-nearest-ties-to-even (assuming default rounding mode)20:57
programmerjakesee fsts (f32 store) pseudocode for an example20:58
markosI see, yes, it makes perfect sense, I'm sure I got bitten by the rounding in some numbers21:00
programmerjakeactually, if the input is already a f32 in f64, rounding will have no effect (except signalling -> quiet NaN conversion)21:01
markosthen it was too the effect of incorrect indices for d021:05
markosanyway, I'm glad it got fixed21:05
programmerjakeyeah, probably21:05
programmerjakeoh, another difference: SINGLE is part of the PowerISA v3.1B spec, DOUBLE2SINGLE isn't21:14
octaviusmeeting lkcl22:00
lkclprogrammerjake, yes they're all part of the Power ISA spec. i just didn't put SINGLE() in fphelpers.mdwn22:01
lkcldef SINGLE(FRS):22:01
lkcl    """convert incoming FRS into 32-bit word.  v3.0B p144 section 4.6.322:01
lkcl    """22:01
markoslkcl, updated ticket with numbers23:02
markosmight be off by a few23:03
markosbut really only a few23:03
programmerjakei'm going to skip the librebmc meeting today, i have other stuff i need to do23:04
markoslkcl, mind you that's intrinsics, not asm instructions, for Arm case it will make a difference as eg. ADD may have multiple intrinsic variants (vaddq_{s|u}{8|16|32|64}) but it's still considered one asm instruction with multiple forms23:06
markosit's still a lot of instructions though, the only thing that saves arm development is that it's orthogonal and easy to remember/predict the name of an intrinsic23:07
markoswhich isn't the case with Intel23:08

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