Tuesday, 2022-07-26

markosok, finally, fmvis tests pass, I'm able to load float immediates, I couldn't make it work before because I was stupidly trying to make it work with expected_regs, but I needed to use expected_fprs :)10:18
markoslkcl, I'm ready to commit, I saw in the bug report that you want me to commit minor_22.csv separately, but the rest should all go in one commit, right?10:18
markosie, test cases, etc10:18
lkclmarkos, doh :)10:58
lkclif you've everything just commit it10:59
markosok11:00
markosuhm, I still have the https git url11:04
markosis there a git+ssh or should I do https auth?11:05
markosI think I've already sent the ssh pubkey11:05
programmerjakeassuming you mean openpower-isa.git, just use ssh://gitolite3@git.libre-soc.org:922/openpower-isa.git11:13
programmerjakejust replace the https url in .git/config11:13
markosyup, that one, this worked, thanks11:14
markosgit commit 51ebd2111:15
programmerjakeyw11:15
markosok, first commit, so if I've done anything really bad, please be gentle :)11:15
programmerjakeci in case you're curious: https://salsa.debian.org/Kazan-team/mirrors/openpower-isa/-/jobs/303870611:19
programmerjakeci was broken before, so, no, you're not responsible for having broken it11:27
markosah nice11:51
markosgood to know11:52
markoswhat CI software is this?11:52
markosbeen struggling with jenkins so far, it gets the job done but when I try to do anything advanced I get in trouble11:53
markosah wait, I only did the fmvis, not the 2nd half variant11:54
lkclmarkos, fantastic, i'll take a look shortly, i'm just in the middle of replying to jacob bachmeyer12:01
lkclprogrammerjake, thx for sorting things for markos12:02
markosnow that I got the hang of it, what's the 2nd variant supposed to do?12:02
lkcljb was on the riscv-isa-dev mailing list back in 2018 (and even before)12:02
lkclloading in the lower half immediate into the same register you just wrote the top half into12:02
lkclso it's actually a read-modify-write instruction12:03
markosbut keeping the first half?12:03
markosso essentially with a fmvis+ 2nd variant one can load a full 32-bit float constant?12:04
markoswhat's the name of the 2nd variant again? :)12:04
lkclyes.12:06
lkcl*not* fishmv :)12:07
markosfmvish?12:07
lkclhttps://libre-soc.org/openpower/sv/int_fp_mv/12:07
lkclhaha i like that one12:07
lkclsooort-of vaguely, if you maybe feel inclined, mv the FP reg for me?12:08
lkcli *think* i have added RS as an "OUT" for you already, in advance, here.... 1 sec...12:08
markossure, just tell me where to do that, things have changed in the code lately as I see12:09
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_enums.py;h=a5e928806aedae9ce3cae898fd744cd693c5f7f7;hb=51ebd21c50d53275e8dd828a997433175b6dd2a2#l52012:09
lkclyep, all good12:09
lkcland it's also an in112:10
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_enums.py;h=a5e928806aedae9ce3cae898fd744cd693c5f7f7;hb=51ebd21c50d53275e8dd828a997433175b6dd2a2#l47412:10
lkclso this is relevant for the minor_22.csv12:10
lkclyou need to specify RS *twice*12:10
lkclonce in the in1 column12:10
lkclonce in the out column12:10
markoslike in fmvis12:10
markosyou mean FRS12:10
lkclah, yes, sorry.12:11
lkcl1 sec...12:11
lkcldid i add FRS to out? yes12:11
markosI guess so, otherwise the tests wouldn't pass :)12:11
lkclahh... err... fmvis it's both an in and out? that's... err...12:11
markosyou said I had to do that12:12
markosas in1 can't be an SI12:12
lkclrrright, ok, fmvis is not a read-modify-write because the upper parts are zero'd12:12
lkclyes, but i was probably referring to fishmv needing to be read-modify-write not fmvis, apologies if that wasn't clear12:12
lkclit does mean that you can literally cut/paste the fmvis line in minor_22.csv though :)12:13
markosok, that's good12:13
markosbut I'm confused, which one is it now, fishmv, frlsi or fmvish? :)12:13
lkclbut you _will_ have to recompile (pywriter noall av)12:13
lkclfrlsi.12:14
markosok, yes ofc12:14
lkclas in the spec12:14
lkclthe pywriter compiler actually reads all of the CSV files in order to identify which registers are read and which are written to12:14
lkcland actually creates function-call parameters with the incoming registers as arguments if they are in in1/2/3.12:15
lkclso what you should find, if you inspect decoder/isa/av.py, is that after making in1=NONE for fmvis, that the RS argument magically disappears12:16
lkclhave you looked at the auto-generated compiler output from pywriter at all? i occasionally put in debug print() statements in it to see what the hell's going on12:17
markosyes all the time, that's how I found out that the FRPs were actually changed by fmvis :)12:19
markosit's hard to follow, but all the info is there12:20
markosinteresting12:21
markosthese 2 make for an interesting feature12:21
lkclyeah, i made sure every bit-level operation is dumped out, because, well, this is the only way you find out if you made bit-level mistake12:22
lkcls12:22
markosyou could load the top-half of some constants12:22
markosand with flrsi you could use the result of fmvis and generate a ton of fp full constants with the lower-half changing only12:22
markoswhere FRS is different than RS12:23
markoser, where OUT != IN112:23
markoshm, wait12:24
markosa few days ago, you told me to use 3 operands, now I see 212:24
markosin fact, flrsi could use 312:24
markosflrsi OUT, IN, imm12:25
markosand IN might be different than OUT, for the above reason12:25
markoseg. say you have the following constants12:25
markos0x41298733 and 0x4129874212:25
markosfmvis would load 0x41290000 to eg. reg 312:26
markosand you use flrsi 4, 3, 0x8733 and flrsi 3, 3, 0x874212:26
markosand voila12:26
markosyou have 2 fp constants loaded with 2 instructions only12:27
lkclno, there's nowhere near enough space in 32-bit to do that. unfortunately.12:27
lkclhence why flrsi is an (extremely rare / unique) load-modify-write12:28
markosok, I see12:28
lkcl+    # V3.0B 1.6.6 DX-FORM12:28
lkcl+    # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |26|27    |31  |12:28
lkcl+    # | PO   |   FRS         |     d1      |      d0     |   XO |d2  |12:28
lkclwhere would the 2nd register fit?12:28
lkcl16-bits of immediate is *really* expensive12:29
markosah I see12:29
lkclthere's such an insane amount to consider with ISA development!12:31
markosok, I fixed minor_22.csv and put NONE for in1, changed the syntax, ran the sv_analysis, power_fields.py, etc but now the test complains that I supplied 2 values instead of 3, what do I have to update?12:44
markosnever mind12:45
markosstupid me, found it12:45
lkcl:)12:45
lkclfunny this IRC chat system isn't it.12:45
lkclit's like a magic debug system12:45
lkclyou only have to type out the problem and voila! you find the solution!12:46
lkclghostmansd[m] was doing that routinely, a few months back12:46
markosfor it's been years and I'm still doing it12:46
markos^for me12:46
ghostmansd[m]lkcl, markos, yeah I'm probably the most affirmative example this magic system works12:50
lkclmarkos, do drop that in as a separate commit *before* proceeding to flrsi, with suitable explanation12:51
lkclit's definitely fitting the "one purpose, one commit".12:51
lkclwhere the previous one was also same, and nice, because it's everything-in-one.12:51
lkcli'm going to add it to the list of examples "how to add an instruction"12:52
lkclgeneral rule, if you're ever tempted to use the word "and" in a commit message, stop immediately :)12:54
* lkcl frickin mental headache, have to deal with it12:55
ghostmansd[m]> stop immediately12:56
ghostmansd[m]...and use a semicolon, for God's sake!12:56
* lkcl snorts13:22
markoshm, no, that wasn't it, apparently method av() in svp64.py needs 3 operands (RT, RA, RB), so if I want just 2, then I have to provide my own method or I am missing something13:39
markosand I did wrong anyway, because I have added fmvis both in the custom_insns array AND the list of insns handled by av13:43
markosobviously the av one worked as it was able to handle the conversion automatically13:43
markosbut needs 3 operands13:44
markosFile "/home/markos/src/openpower-isa/src/openpower/sv/trans/svp64.py", line 324, in av13:44
markos    (RT, RA, RB) = fields13:44
markosValueError: not enough values to unpack (expected 3, got 2)13:44
markosI think I got it13:56
lkclmarkos, av is specifically designed for the group of instructions maxs/maxu/minu etc.14:08
lkclwhich very specifically are X-Form14:08
lkcldon't for goodness sake try to use the av() function for anything else14:08
lkclfor (name, XO) in (14:10
lkcl            ("maxs"   , 0b0111001110),14:10
lkcl...14:10
lkcl...14:10
lkcl    CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)14:10
lkcli see what you've done14:11
lkclyou added *two* decoders.14:11
lkcl1.14:11
lkclCUSTOM_INSNS = {}14:11
lkclfor (name, hook) in (14:11
lkcl            ("fmvis", fmvis)14:11
lkcl        ):14:11
lkcl    CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)14:11
lkclwhich is the correct location14:11
lkclnotice how functools.partial applies the extra arguments?14:13
lkcl(this is python higher-order-programming btw, i've not really used functools.partial before, i'm not so keen on it but it works)14:14
lkclbasically it creates a function which calls a function but adding extra arguments specified as *args to partial14:14
lkcltherefore if you have this:14:14
markosyes, fixed it now and added custom_insn for fmvis and it works ok now with 2 operands14:14
lkclexcellent.14:14
lkclyou should really just have14:15
lkcl     CUSTOM_INSNS["fmvis"] = fmvis14:15
lkclbecause there's no Rc=1 mode for fmvis14:15
lkcland remove this as well14:16
lkclfor (name, XO) in (14:16
lkcl            ("fmvis"  , 0b0000000011),14:16
lkcl <------14:16
lkcl        ):14:16
lkcl    CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)14:16
lkclwhoops14:16
lkcl            ("fmvis"  , 0b0000000011), <-----14:16
markosyup, done14:17
lkclmagic14:17
lkclafter a while it kinda makes sense, you know?14:17
markosit does14:17
lkclghostmansd[m] did the synthesis of those parsers.  a few weeks ago trans/svp64.py was a bucket-load of repeated cut/paste code14:18
lkclstrictly speaking *all* of those can (and really should) be replaced by fully-automated parsing14:18
lkclafter all, those fields (and offsets) are straight out of the machine-readable fields.txt file14:18
lkclthe gotcha is the XO Field is not.14:19
lkclwhich is in the CSV files in a not-so-easy-to-get-at format14:19
ghostmansd[m]This all should be generated, yes. I mentioned it that many times that I cannot even count.14:20
ghostmansd[m]But this needs that much time to do it elegantly that I surrendered.14:20
lkclin power_decoder.py if the XO-opcode-recognition can be recognised then it should be doable14:20
ghostmansd[m]But, on the other hand, I simply could not look at these copy&paste anymore, especially considering it was wrong in some parts.14:21
lkclsigh, yes.14:21
ghostmansd[m]So I did something intermediate: a hack which simplified it at least somewhat.14:21
lkclwe broke the rule not to have everything auto-generated.14:21
lkcli started as a quick hack to add one instruction and it kinda got out of hand :)14:21
ghostmansd[m]Yeah. Anyway, we still can generate it. Even if we broke the rule, we should unbreak it eventually. :-)14:22
markosok, committed a fix, tht should do it14:22
markosnow on to flrsi14:22
ghostmansd[m]And I have ideas and plans on this part.14:22
ghostmansd[m]Because, after all, this _is_ our reference.14:23
ghostmansd[m]I mean pysvp64asm.14:23
lkclmarkos, fantastic, looks great14:23
lkclghostmansd[m], muhahahah.14:23
lkclyes it is14:23
lkclit's also supposed to be the easy way to check that the spec's correct.14:24
ghostmansd[m]Yes, exactly.14:24
ghostmansd[m]And, even, if it wasn't... anything that can be generated must be generated.14:25
ghostmansd[m]Programmers are notoriously bad ad typing the stuff by themselves. If this crap can be grouped in one place, and be propagated to other pieces by means of generator reusing the common code, this is much better: we'll end up with single source of truth.14:27
lkclmarkos, ah - just looking at these https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/alu/fmvis_cases.py;hb=HEAD14:29
lkclPower ISA stores FP32 numbers in *FP64* format14:29
lkclhence why, if you look at the pseudocode in https://libre-soc.org/openpower/sv/int_fp_mv/14:30
lkcli put this:14:30
lkclbf16 = d0 || d1 || d214:30
lkclfp32 = bf16 || [0]*1614:30
lkclFRS = Single_to_Double(fp32)14:30
lkcland that's almost exactly the pseudocode that needs to go into av.mdwn14:31
lkcl(ok bf16 <- d0 || d1 || d2)14:31
lkclalso14:32
lkclit's DX-Form, where you've added X-Form14:32
markosso the checks need to check against 64-bit values?14:32
lkclyes14:32
markosapologies, probably left-over from copy-paste14:32
lkclok i am just about waking up now (cutting through a lot of pain)14:32
lkclhttps://libre-soc.org/openpower/sv/int_fp_mv/14:33
lkclfmvis fits with DX-Form:14:33
lkcl0-56-1011-1516-2526-3031Form14:33
lkclMajorFRSd1d0XOd2DX-Form14:33
lkclwhere in https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/av.mdwn;hb=HEAD14:33
lkclyou have added it as X-Form14:33
lkcl 211 X-Form14:33
lkcl 21214:33
lkcl 213 * fmvis FRS,SI14:33
markosfixing this now14:33
lkclthe Single_to_Double function i got the wrong name14:34
lkclit *should* be dropped into the namespace of the compiled code, av.py, via an @decorator, from helpers.py14:34
* lkcl can't off top-of-my-head recall the full details, 1 sec14:35
lkclok i don't think we have a DOUBLE2SINGLE function urrr14:36
lkclwait, ah! yes14:36
lkclit's, ha, from the Power ISA spec14:36
lkcland is again auto-generated via the compiler, ha. been 8 months since i did that.14:37
lkcl./openpower/decoder/isafunctions/double2single.py:    def DOUBLE2SINGLE(self, FR):14:37
lkclhang on... sorry, that's double2single, you want single2double14:38
lkclah screw it14:38
lkcljust drop the bits into the right places :)14:38
lkcl    e = FRS[1:12]14:38
lkcl    m = FRS[12:64]14:38
lkcl    s = FRS[0]14:38
markosI think it should be e = FRS[1:11]14:40
lkclyes, that was python numbering14:41
lkclah damnit it does need conversion.14:42
lkclfrickin frick. where's that damn function, i know it's around somewhere14:42
lkclgot it.14:43
lkcljust "DOUBLE()"14:43
markoson it now14:45
* lkcl updating the wiki page to match14:46
lkclsome context: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isafunctions/double2single.mdwn;hb=HEAD14:49
lkclthese are actually extracted from the Power ISA spec14:49
lkcl(Appendix A.1 Book I)14:49
lkcland they're, surpriise, machine-readable executable code.14:49
lkclyou can see the results in openpower/decoder/isafunctions/double2single.py14:50
lkcland those three functions all get dropped into the namespace of the simulator for you to use14:50
lkclby... mmm...14:50
lkclmultiply-inheriting in ISACaller, i believe14:50
lkclif you have a look at test_caller_svp64_dct.py14:51
lkclyou'll see how i hack-job-instantiated a *separate* helper instance in order to get at the damn functions "stand-alone", so as to be able to use them to test the expected results14:51
lkclotherwise you have to piss about doing the bit-level decoding manually14:52
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_dct.py;hb=HEAD14:52
lkclinitially i was really dismayed by what IBM's done here, storing FP32 in FP64 format14:53
lkclbut then i realised that, actually, you can *use* the FP32 instructions as "faster" ones when accuracy doesn't matter...14:53
lkcl... oh and not have to piss about with explicit opcodes converting from FP32 to FP64 and back, the data's *already and always* in FP64 format, in the FP registers14:54
markosok, committed a fix, tests pass now, form, pseudo-code fixed and test values are now 64-bit14:58
markosI *think* I have got it right this time14:59
markosok, eureka moment, initially I thought that av.mwdn was "just" documentation, now I realized that it actually autogenerates the code for the instructions, duh15:10
markosok, just realized that it's veeeery easy to mistype frlsi to flrsi and waste many minutes trying to figure out the problem15:31
markossince we're in the design phase, I'd suggest we change the name15:31
markosit was right in front of my eyes and I kept missing ti15:31
markosit15:31
lkcli really like fishmv :)15:42
markoswhen is RM-2P-1S1D.csv updated?15:43
lkclyees, hooray, you got it - yes it's really *not* "just documentation"15:43
lkclwhen you run sv_analysis15:43
markosok, because something must have been fixed with the latest changes and it's now removed from there15:43
lkclwhich creates CSV files, which we then commit. it's one of the extremely rare circumstances for committing auto-generated output15:43
lkclif it's removed then it's simply not a recognised pattern by sv_analysis.py15:44
lkclwhich i'll have to fix15:44
lkcl1 sec15:44
lkclleave it with me15:44
lkcl+DX-Form15:45
lkcl15:45
lkcl * fmvis FRS,SI15:45
lkcl15:45
lkclyou need to update the declaration of fmvis as well15:45
lkcl(again, because, as you appreciated, now, that's used by the compilers)15:45
markosapologies for bothering you with all that seemingly trivial stuff, but really it's all new to me15:46
lkclbut... ehmmm... 1 sec...15:46
lkclhave to find a DX-Form instruction in the Power ISA spec...15:46
lkcladdpcis15:46
lkclah.15:46
lkclok15:47
lkclit does actually reconstruct D manually. damn.15:47
lkclthat's really annoying of the ISA architects to have done that15:47
lkclp66 Power ISA v3.0C15:47
markos+1 for fishmv btw, much harder to mistype this15:50
lkclplus, mikey liked it https://twitter.com/lkcl/status/153236360671681740815:51
markosso, ok to commit RM-2P-1S1D.csv with removed fmvis?15:55
* lkcl something odd going on with fmvis15:55
markosor is there something missing?15:55
* lkcl tracking it down15:55
markosI have the suspicion that I'm doing the expected_fprs handling in the wrong way15:55
lkcllook at test_caller_svp64_dct.py for how it should be handled15:56
lkcli'm not getting any debug log messages15:56
lkclleave it with me to investigate15:56
markosok15:56
lkcl   post-processed name NONE .long NONE15:57
lkclillegal .long NONE15:57
lkclah that's a clue15:57
lkclXO=00011 all good...15:59
lkclok, the fmvis function in svp64.py, annoyingly, is an exception-to-the-rule16:00
lkcleverything else is clean but this one isn't, sigh16:01
markoswhat did I do wrong?16:04
lkclnothing i could have predicted, 1 sec16:04
lkclthe only other DX-Form instruction, addpcis, is one that's not been implemented yet16:05
lkclno don't commit the sv_analysis csv change16:07
lkcli reverted the removal of FRS as in116:07
lkclFRS is definitely an in116:07
lkclwait...16:08
lkclfrick16:08
lkclno you're right16:08
lkclmarkos, fyi, have a look here16:09
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=c23a608e97a14e18564e806f1a2921cdeb07960616:09
lkcli'm still working out why it's call .long NONE16:10
lkclobviously that should be call fmvis in the log output16:10
lkcltime to print out the binary of an fmvis instruction....16:10
markosdamn16:11
lkclopcode, fields substed ['fmvis', '5,65535'] fmvis ['5', '65535']16:11
lkclfmvis 0b101100010111111011111111110011116:11
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=47835dbedc58dfab1ec1643981f76a478610fa7216:12
lkclreally we should have unit tests in svp64.py not these hand-botch-jobs i started adding 2 years ago16:12
lkclahh i think i know what it is16:13
lkclthe pattern-recognition in minor_22.csv is from bits 21..3116:13
lkclXO for fmvis is in bits 26 to *30* not 26 to 31...16:14
lkcland you have:16:14
lkcl------00011,ALU,OP_FMVIS,FRS16:14
lkclthat's offset by one16:14
lkclit should be16:14
lkcl-----00011-,ALU,OP_FMVIS,FRS16:14
lkclhooray! now we are cooking with gas16:15
ghostmansd[m]Folks, am I right that you're adding a new instruction to svp64.py?16:15
lkclghostmansd[m], yyyep.16:16
lkclfmvis.16:16
ghostmansd[m]> hooray! now we are cooking with gas16:16
lkclmarkos, https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=1e6d95e1658526d2bda5a7b2714c3d735e8eee0716:16
lkclghostmansd[m], ha ha16:16
ghostmansd[m]lkcl, you're literally pushing me to make a joke about Gazprom16:16
lkclit's an english expression16:16
lkcldon't hold back...16:16
ghostmansd[m]:-D16:16
ghostmansd[m]We actually also call it gas16:16
ghostmansd[m]Or, rather, gaz16:17
ghostmansd[m]But pronounced the same16:17
lkclhttps://www.urbandictionary.com/define.php?term=cooking%20with%20gas16:17
ghostmansd[m]Wow16:17
lkclhttps://english.stackexchange.com/questions/25897/origin-of-the-phrase-now-were-cooking-with16:17
ghostmansd[m]For me cooking with gas is quite fast, to be honest16:17
ghostmansd[m]Ah OK got it16:18
ghostmansd[m]Funny16:18
lkclit dates back to 1940s apparently, when gas stoves started replacing wood stoves in 191516:18
lkcl:)16:18
ghostmansd[m]Ok, so you need the new insn in gas, right?16:18
lkclyyeah, we do16:19
* lkcl head spinning slightly...16:19
lkcltoo many things at once16:19
lkclmarkos, a quick debug-print in av.py, you'll be delighted to hear, is producing the right answer(s)16:21
lkclhttp://weitz.de/ieee/16:22
markoshooray!16:22
lkclnot actually being checked though, working that out16:25
lkclmarkos, can i leave it with you to add what 0x2122 is, in FP?16:28
lkcli need to add fprs to ExpectedState16:28
markosyes, I've added more tests that involve common fp constants like pi, etc16:28
lkclhttps://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/test/state.py;hb=HEAD16:29
lkclplease do a git pull16:29
markosftr, pi is 0x400921fb54442d18 in 64-bit :)16:29
lkclthe only reason it's "passing" is because ExpectedState() has zero GPRs16:29
lkcland this instruction doesn't modify GPRs16:29
markosI thought that expected_fprs was not doing what I thought it did16:30
markosI'll follow the tests from svp6416:30
lkclyou're passing it in as the first argument to add_cases() which is actually the GPRs16:31
lkclyes good idea.16:31
lkclit's very different (and slower) but probably a better first template to use16:31
lkclincluding the _check_regs() function whih you can see in test_caller_svp64_dct.py16:32
lkclhaha i love that you know pi in IEEE754 hex format16:32
lkclactually, can you leave it as-is>16:34
lkcl?16:34
lkclit will make a good test of the ExpectedState modifications i'm just doing16:34
markosI think I'll change 0x2122 turns out it's a ridiculously small number, 4.19e-32016:35
markoswas just a random hex value I entered16:35
lkclridiculous numbers are good!16:35
markosok then16:36
lkclokaay done16:37
lkclcan you take a look?16:37
markoslooking at it now16:38
lkclequal (expected) '.long 0x58e01f46'.  got 3c00000000000000  expected 4000000000000000 at pc c 416:39
lkclhooray!16:39
lkclfp reg 5 is detected as an incorrect value!16:39
markos:)16:40
lkclthat's odd (and almost certainly wrong)16:40
lkclhttp://weitz.de/ieee/16:40
lkcl0x3C0000000000000016:40
lkclis 1.0842021724855044E-1916:41
lkcltime to put some debug-prints in av.py16:41
lkcl    def op_fmvis(self):16:42
lkcl        print ("d0 d1 d2", d0, d1, d2)16:42
lkcli get16:42
lkcld0 d1 d2 SelectableInt(value=0x80, bits=10) SelectableInt(value=0x0, bits=5) SelectableInt(value=0x0, bits=1)16:42
lkcld0 is 0x80 which is 0b1000_000016:43
lkcl8-bit16:43
lkclwhen converted to FP32 that ends up as16:43
lkcldouble SelectableInt(value=0x20000000, bits=32)16:43
lkclwhich is wrong16:43
lkclit should be 0x4000_000016:43
lkcli almost certainly have an off-by-one in svp64.py16:44
lkclone of these16:44
lkcl    # first split imm into d1, d0 and d2. sigh16:44
lkcl    d2 = (imm & 1) # LSB (0)16:44
lkcl    d1 = (imm >> 1) & 0b11111 # bits 1-516:44
lkcl    d0 = (imm >> 6) # MSBs 6-1516:44
markosok, I can work it out if you like16:44
lkclyes please16:44
markosnp16:44
lkclnow we've got feedback it should be a breeze16:44
markosyup, same with flrsi/fishmv :)16:45
lkclsorry, i didn't know that DX-Form was non-standard16:45
lkclyes. should be plain sailing from here16:45
lkclghostmansd[m], another english expression16:45
markosit's ok, glad to have offered the incentive to implement this :)16:45
lkclhttps://dictionary.cambridge.org/dictionary/english/be-plain-sailing16:45
lkcl:)16:45
lkclit would have made my life easier for test_caller_svp64_dct.py as well, sigh16:46
markosmaybe intime refactor some of that code around it, it would help me learn the code in depth too16:49
markoslkcl, ok I see a possible issue in DOUBLE()17:58
tplatenI assume that an IcarusOrangecrabPlatform is needed, since I want to simulate the changes needed for OrangeCrab.17:59
markosI'm setting the immediate value to 0x4009 which if converted to double 0x4009000000000000, it would convert to 3.12517:59
markosbut double converts it to value=0x400120000000000018:00
markosI checked the av.py code and added some prints18:00
markosprint("d0, d1, d2", d0, d1, d2)18:00
markos        bf16 = concat(d0, d1, d2)18:00
markos        print("bf16", bf16)18:00
markos        fp32 = concat(bf16, concat(0, repeat=16))18:00
markos        print("fp32", fp32)18:00
markos        FRS = self.DOUBLE(fp32)18:00
markos        print("FRS", FRS)18:00
markos        return (FRS,)18:00
markosbf16, fp32 print out fine, 0x4009, 0x4009000018:00
markosbut FRS gives the wrong value18:01
tplatenIm now comparing gram/gram/simulation/crg.py with ls2/src/ecp5_crg.py, then18:20
tplatenadding support for the simulated orangecrab to gram/gram/simulation/crg.py18:23
programmerjakemarkos, 0x4001200000000000 is the correct double value for immediate 0x4009, the immediate is the top half of f32, not f64. i can't tell if you already figured that out...19:10
programmerjakethat's because f64 has a larger exponent field19:13
tplatenIm had a look at ECPIX5CRG and found out that a19:21
tplatenSynchronous Release Global Set/Reset Interface19:21
tplatenInstance("SGSR", i_CLK=ClockSignal("rawclk"), i_GSR=gsr1)19:21
tplatenIn ls2 no SGSR is used, reset is handled a different way19:21
tplatenno I was wrong, it is used, but where does the reset signal come from on the orangecrab19:23
tplatenand part of the crg code is duplicated, that makes everything hard to maintain.19:27
tplatenclass PLL is also duplicated, I was unable to see any changes here. But in the CRG there are too many changes19:45
ghostmansd[m]lkcl, so, on binutils side, the next targets are: 1) sync with svp64.py again; 2) support prefix for disassembler; 3) test svp64.py and binutils20:04
ghostmansd[m]That's w/o opening the tasks in bugzilla, just as I recalled; everything correct?20:04
lkclghostmansd[m], looks about right, although not having bugzilla tasks makes me twitchy20:17
lkcli wonder...20:17
lkcli think we can get away with raising a new binutils budget under the cavatools grant20:17
lkclmarkos, that's why i used the helper-routines in test_caller_svp64_dct.py (and others) because you can perform FP64-hex to python-float and check what the hell's going on20:50
markosprogrammerjake, if it was a larger value perhaps, but 0x4009/3.125 has exponent set to 1.0 so I don't think this is a correct explanation21:45
markosin fact, setting manually a double value to 0x40012 produces a double close to 2.1406221:48
markosso it's definitely not a correct double value21:49
markossorry, I meant setting it to 0x400120000000000021:49
markosanyway, I'll investigate this further21:51
octaviusmeeting in 8min markos, programmerjake, toshywoshy, cesar21:52
programmerjakebut bf16 0x4009 *isn't* 3.12522:34

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