Thursday, 2022-08-25

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programmerjakelkcl: found an inconsistency: offset is added before indexing here, but is added after indexing in the code below that adds elwid overrides to the index vector: https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/remap.mdwn;h=4e0e6100a8c1d1e10d23ac0b747042223063be5c;hb=272b57dc85cbab7839ef902977e4f11a7b32c390#l40303:01
lkclwell spotted03:11
lkclshould be03:11
lkcl 403     return GPR((SVSHAPE.SVGPR<<1)+i)+SVSHAPE.offset03:11
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programmerjakeI think I got openpower-isa to pass on CI now, just have to wait and see if I'm right.10:41
programmerjakelkcl: several of the tests I marked need to be inspected in https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=3dbb94d9509042cb03092a392fd9dd82b0a7c8d710:42
programmerjakemostly test_minor_30 in test_power_decoder10:42
programmerjakemost the rest of the tests I marked just look like they're not super important and have just bit-rotted10:43
programmerjakeI had to re-fix the sv assembler, since you rewrote my change to get sv.andi. to work, your change apparently broke sv.add.: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=457a6cd533e85f0961b858d2679fd96218e9662f10:45
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kanzurehttps://github.com/WebAssembly/design/issues/105014:43
programmerjakeneat!14:47
lkclprogrammerjake, good catch. long day yesterday.15:20
lkcl-        # get regs info "RT, RA, RB"15:20
lkcltry not to remove comments, eh? :)15:26
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programmerjakei moved that comment to the end of the line:23:29
programmerjake+        v30b_regs = isa_instr.regs[0]  # get regs info "RT, RA, RB"23:29
programmerjakeso, no, i didn't remove it23:29
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