lkcl | programmerjake, ah brilliant, thx | 01:37 |
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lkcl | i thought initially all implicit-RS-behaviour would be consistent and identical across all instructions | 01:38 |
lkcl | turns out it's not. | 01:38 |
lkcl | fft-mul-add-subtract needs to source implicit-RS from *RB* | 01:38 |
lkcl | (urr...) | 01:38 |
programmerjake | well, I designed the bigint instructions with the assumption that it's just like the fft ops... | 01:39 |
programmerjake | as you explained previously | 01:39 |
lkcl | unfortunately that would mean they'd need to be implicit-RS-from-*RB* | 01:39 |
programmerjake | where RS=RT+MAXVL or RS=RC | 01:39 |
programmerjake | why not define it to be RS=last-reg-arg rather than RS=RC or RS=RB? | 01:40 |
lkcl | in the FFT ones, RS=RB+1 or RS=RB+MAXVL | 01:40 |
programmerjake | wait, RB+1?!! | 01:40 |
lkcl | yyep | 01:40 |
lkcl | sigh | 01:40 |
lkcl | something like that | 01:40 |
programmerjake | magic annoying exceptions... | 01:41 |
lkcl | it's 1:40 am so i'm not entirely "up-and-about-in-code-hunting-and-examining" mode | 01:41 |
lkcl | the logic is embedded in PowerDecoder2 | 01:41 |
programmerjake | well, as long as all the bigint ops can still use RS=RC (in SVP64 mode) and (in scalar mode) RS=RT+1, I'm happy. | 01:42 |
programmerjake | go work on it another day :) | 01:42 |
lkcl | :) | 01:44 |
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ghostmansd[m] | markos, I found that fmvis/fishmv are not in binutils at all. We only supported fptrans added recently by programmerjake. I remember I had some dances with these in Python, in disassembly, but these are not in binutils yet. Can you raise the task, please? I think I'll support these in a day or two. | 09:01 |
ghostmansd[m] | binutils lack a lot of other stuff added recently too. | 09:02 |
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markos | sure, will do that | 09:04 |
ghostmansd[m] | I'm not sure what'd be the exhaustive list, so I'll have to add some code in binutils which prints the supported instructions, then compare it with the output from some script which traverses our stuff. | 09:05 |
ghostmansd[m] | I'll support fmvis/fishmv first, since these block your work, but actually we have way more instructions missing. Unfortunately these instructions mostly require manual intervention due to the way binutils so these tricks. | 09:07 |
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markos | ghostmansd[m], https://bugs.libre-soc.org/show_bug.cgi?id=945 | 09:29 |
markos | thanks again | 09:29 |
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lkcl | markos, ghostmansd[m], am just linking that to as many things as i can find. it's the first one that we are submitting as an external RFC for example | 11:47 |
lkcl | daaang that DDOS attack is still ongoing and it's so bad that some routes across the internet are completely overloaded | 11:50 |
lkcl | from different countries to the same site is "fine" | 11:50 |
lkcl | saw this last happen around 2018, i was in shenzhen at the time, *all* internet traffic between europe and the uk had to be routed via a meagre connection through sweden or something like that | 11:51 |
lkcl | i was getting 10-15k/sec | 11:51 |
lkcl | this is waay worse | 11:51 |
ghostmansd[m] | lkcl, what do you mean about linking? | 12:08 |
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lkcl | stand-alone bugreports get completely lost, only findable by accident on keyword searches | 14:47 |
lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=945 is now linked to | 14:47 |
lkcl | 944 - the OPF ISA RFC ls002 | 14:47 |
lkcl | 887 - the implementation in ISACaller that markos did | 14:48 |
lkcl | 650 - the specification page containing all the int <-> fp mv instructions | 14:48 |
lkcl | 939 - cavatools which is where the funding is likely to come from for the addition of these two instructions | 14:48 |
lkcl | "linked" | 14:49 |
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ghostmansd | lkcl, https://bugs.libre-soc.org/show_bug.cgi?id=946 | 15:24 |
ghostmansd | markos, I've starting to move the fish :-) | 15:25 |
* ghostmansd always wants to make some joke about fishmv instruction | 15:27 | |
ghostmansd[m] | lkcl, sorry, I missed the message about linkage. I'll link 946 there too. I left you as assignee, this task will need some intervention on CSV level. | 15:29 |
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lkcl | well i also would love the other one to be "fli" - float-load-immediate | 15:58 |
lkcl | "flis" - float-load-immediate-shifted is better, based on "oris" | 15:58 |
lkcl | which is "or immediate shifted" | 15:58 |
lkcl | so we have "fli fishmv" or "flis fishmv" | 15:58 |
lkcl | :) | 15:58 |
markos | lol, reminded me of FLDSMDFR | 16:24 |
markos | for those who like cartoons :) | 16:24 |
programmerjake | well, if we're naming consistently, it would be something like flish rather than fishmv, or frlhsi/frlhoswi (fp replace lower half of single with immediate) | 16:30 |
programmerjake | or maybe just keep it simple: fli2 -- fp load immediate 2nd-step | 16:33 |
programmerjake | which makes you want fli3 and fli4... | 16:34 |
programmerjake | fli3: RT <- SINGLE(RT) || imm || [0]*16 | 16:36 |
programmerjake | fli4: RT[48:63] <- imm | 16:37 |
programmerjake | so flis; fli2; fli3; fli4 ends up being simply the 4 16-bit quarters of the final fp64 in sequence from msb to lsb | 16:39 |
programmerjake | and to do a whole fp64 with ext001 64-bit ops would just be pflis pfli3 | 16:41 |
programmerjake | pflis is a whole f32, pfli3 is RT <- SINGLE(RT) || imm[0:31] | 16:43 |
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lkcl | https://twitter.com/ppcinstructions/with_replies?lang=en | 17:23 |
lkcl | mficofsr - Move From Is Computer On Fire Status Register | 17:23 |
lkcl | i think it's important to be on that list :) | 17:23 |
lkcl | twerk - Trap Word Extended and Rotate Keyboard | 17:24 |
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programmerjake | fli[s234] are serious suggestions... | 17:24 |
lkcl | eieio is already a serious instruction! | 17:25 |
programmerjake | yes, but you bringing up joke suggestions immediately after my more serious suggestion makes me feel you're treating it as a joke... | 17:27 |
lkcl | sorry | 17:31 |
lkcl | i'd like to prioritise instruction names that are funny | 17:31 |
lkcl | correction | 17:31 |
lkcl | i'd like to *seriously and in all seriousness* prioritise instruction names that are funny | 17:31 |
lkcl | they are more memorable to people, as mnemonics | 17:32 |
programmerjake | i'd like to prioritize instruction names that are easier to understand...imho fli2 is quite memorable because it's similar to li | 17:32 |
lkcl | they also make for better press releases and PR | 17:32 |
programmerjake | and it's the second step of loading fp immediates | 17:33 |
programmerjake | even if they're not your favorite, I'd like them mentioned in future revisions of the RFC since others may like them more, and also they have a logical extension to fli3-4 | 17:45 |
programmerjake | whereas extending fishmv to fithmv doesn't make sense (third half?!) | 17:46 |
programmerjake | also if people are looking for fp load immediate (as is logical from fp ops and li), flis/fli2-4 show up, fishmv doesn't | 17:48 |
ghostmansd[m] | Put your hands off my fish! | 17:52 |
programmerjake | your fish smells funny, it has the odor of confusion... | 17:54 |
ghostmansd[m] | Not until you move it! | 18:31 |
lkcl | can i bang my head against the keyboard yet? | 19:01 |
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lkcl | toshywoshy, btw ping mattermost bridge borked | 19:08 |
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markos | the only problem I'd have against <ins># -type of instructions is that I *always* have to look at the reference to check which variant does which | 19:13 |
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octavius | fli2.... "flee 2" (run away twice as fast)? :D | 19:28 |
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lkcl | haha | 19:37 |
lkcl | ok so the benefit of these instructions unless done as VLE (variable-length-encoding) actually tails off | 19:38 |
lkcl | and Power ISA ain't gonna buy into VLE because it punishes massive-wide multi-issue systems | 19:38 |
lkcl | for a load-quad you have: | 19:38 |
lkcl | sorry | 19:38 |
lkcl | for a load-dword-float you have: | 19:39 |
lkcl | 1 32-bit I-Load | 19:39 |
lkcl | 2 32-bit D-Loads | 19:39 |
lkcl | for a load-immediate-BF16 (fmvis) you have: | 19:39 |
lkcl | 1 32-bit I-Load and THAT IS ALL. covers a huge range and that's why it's always "better" than a load-dword-float | 19:39 |
lkcl | for a load-immediate-FP32 (fmvis+fishmv) you have: | 19:40 |
lkcl | 2 32-bit I-Loads and it is STILL better than a load-dword-float | 19:40 |
lkcl | for a load-immediate-FP64 (fmvis+fishmv+pfishmv) you have: | 19:41 |
lkcl | 4x 32-bit I-Loads because you have fmvis BF16 fishmv FP32 pfishmv extra 32-bit LSBs for the dword | 19:41 |
lkcl | at that point you have reached "sub-par" i.e. are better off using load-dword-float | 19:42 |
lkcl | *unless* it is considered valuable to not hit D-Cache at all with an FP load | 19:42 |
lkcl | if VLE was permitted you could have: | 19:43 |
lkcl | 1 16+64-bit I-Load | 19:43 |
lkcl | i.e. QTY 2.25 32-bit I-Loads | 19:44 |
lkcl | which *would* be better than QTY 1of 32-bit I-Load + QTY 2of 32-bit D-Loads | 19:44 |
lkcl | but doing so "punishes" high-performance multi-issue RISC systems so badly in length-identification on 16/32/48/64/80-bit boundaries that it's just not worth considering | 19:45 |
octavius | Is VLE available on PowerISA? Maybe I just haven't heard you talk about it, but I don't remember seeing it before now. Why even consider it? | 19:46 |
lkcl | bottom line, my feeling is, fmvis+fishmv are definitely worth doing, pfishmv is borderline, and 32-bit extenders for the LSBs aren't worth it | 19:47 |
lkcl | octavius, it was invented by Motorola (Freescale) | 19:48 |
lkcl | they were its primary advocates, users, and implementors | 19:48 |
lkcl | all of which was... 10+ years ago | 19:48 |
octavius | ok | 19:48 |
lkcl | https://www.google.com/search?q=power+isa+vle+book&oq=power+isa+vle+book | 19:49 |
lkcl | i think ST Micro may have been interested in it at one point as well | 19:50 |
lkcl | because of the reduced executable sizes | 19:50 |
lkcl | https://www.st.com/resource/en/user_manual/um0438-variablelength-encoding-vle-extension-programming-interface-manual-stmicroelectronics.pdf | 19:50 |
lkcl | markos, you think you'll do AV1 at all? | 19:57 |
lkcl | reason i ask is, if you can even just put in a report about what you did, and why it was difficult, it *might* be enough to e.g. put in an RFP for EUR 1000 or something | 19:59 |
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markos | I could do that, but it would probably be easier/better to reallocate this 1k to another task | 21:40 |
markos | I'd dislike putting an RFP for something I didn't complete, not even half-way | 21:41 |
lkcl | we don't get the leeway to do that - not without NLnet's permission - and this is the worst possible time to ask (about 7 days left) | 21:47 |
markos | right, ok, I'll give it one last shot over the weekend | 21:48 |
markos | maybe I'll pick a simpler function as well, yuv would be super cool to do, but I don't think there is enough time for this | 21:49 |
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lkcl | hey, even if you can extract something that "looks like" the original c function | 23:23 |
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