Thursday, 2022-10-06

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programmerjakelkcl: important x86 instruction naming correction: https://git.libre-soc.org/?p=libreriscv.git;a=commitdiff;h=b2c4e1cda8831245c4d1b8a98f34174ab5132c8c02:38
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programmerjakeshlq/shrq are the AT&T versions of shl/shr (plain shift), totally different than shld/shrd (double-wide shift). the 32-bit AT&T form of shlq/shrq would be shll/shrl anyway.02:41
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markosghostmansd[m], hi again, another -small I hope- issue with binutils: Error: unrecognized opcode: `fmvis' :)09:37
ghostmansd[m]Hm. I have a vague recall that I added these, but perhaps they're in separate branch.09:38
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lkclprogrammerjake, ack appreciated10:22
lkclghostmansd[m], i need sv.cmp with fail-first so there's some sv_analysis categorisation to do (sv.cmp is not marked as RM.cr_ops but sv.crand and sv.cror are)11:12
ghostmansd[m]IIRC cmp also had some quirks, amirite?11:16
lkclzz and SNZ in RM bits 6-7 but other than that there's only 3 modes (simple,reduce,ffirst) and they fit exactly with RM.normal11:46
lkcli'm going to add sv.cmp to test_pysvp64dis.py to see how it goes11:47
lkclwe got anything to rebase in openpower-isa?11:50
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lkclha that's hilarious: sv.cmp/ff=RC1 *0,1,*4,3 is being recognised as aaaaalll the RM.modes :)  RM.simple, RM.mr, RM.ff3 *and* RM.ff5 are all decoded and printed out :)11:57
lkclah intriguing, it thinks it's an RM Mode None12:03
lkcl    RM12:03
lkcl        None12:03
lkcl        RM12:03
lkcl            00000000001001000000100112:03
lkclok it's when /ff=RC1 is used12:09
lkclsv.cmp *0,1,*4,312:09
lkcl        cr_op: simple mode12:09
lkcl        RM12:09
lkcl            00000000001001000000000012:09
lkclsv.cmp/mr ....12:10
lkcl        cr_op: scalar reduce mode (mapreduce), SUBVL=112:10
lkcl        RM12:10
lkcl            00000000001001000000010012:10
lkcldrat, different mode-bits for cr_ops.12:11
lkclthat explains it12:11
ghostmansd[m]so there's an error in match table?12:14
lkclno, it's back in sv/trans/svp64.py12:14
ghostmansd[m]Ah OK12:14
lkclRM.normal requires mode=0b0112:14
ghostmansd[m]As for about "recognized as all modes"12:15
lkclRM.crops requires mode=0b10|VLI12:15
ghostmansd[m]If no mode found, we get "common RM"12:15
ghostmansd[m]Which incorporates all RM modes12:15
lkclahh nice.12:15
ghostmansd[m]Kinda "union of all RMs"12:15
lkclmakes sense to me12:15
ghostmansd[m]This is mostly caused by the fact that we start with common RM12:16
ghostmansd[m]And then "descend"12:16
ghostmansd[m]We get svp64.prefix.rm12:17
lkclok i'm getting sv.cmp/sz instead of sv.cmp/ff=RC1 gimme 1sec12:17
lkclneed to check sv/trans/svp64.py some more12:17
ghostmansd[m]See mode in vebose disasm12:18
ghostmansd[m]This should help12:18
ghostmansd[m]*verbose12:18
lkcl        cr_op: ffirst 5-bit mode12:18
lkcl        RM12:18
lkcl            00000000001001000001000112:18
ghostmansd[m]See what RM mode is12:18
ghostmansd[m]Aha, so the tables matched CR op, and ffirst 5-bit12:19
lkcli think i know what it is, there's differences in where /sz is placed12:19
lkcl(back in sv/trans/svp64.py)12:19
ghostmansd[m]Might be12:19
ghostmansd[m]See class which corresponds to this mode12:19
ghostmansd[m]And stuff it inherits and it's fields12:20
lkcl        RM.mode12:20
lkcl            1000112:20
lkcl            27, 28, 29, 30, 3112:20
lkclthat's wrong12:20
ghostmansd[m]No-no I mean the code12:20
lkclthat's a fault in sv/trans/svp64.py12:20
lkclnot power_insns.py12:20
ghostmansd[m]Or in the code12:20
ghostmansd[m]Ah OK12:20
ghostmansd[m]Anyway, recheck the bits positions12:20
ghostmansd[m]I might fucked it up12:21
ghostmansd[m]Search for "sz: " and find the class12:21
lkclno unlikely.  CROPs really is different for failfirst12:21
ghostmansd[m]The name will be something like FF512:21
lkclw00t, got it12:35
lkclur not quite12:36
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ghostmansd[m]All fields are declared like "sz: _Field = (10,)"12:48
lkcli got it.12:49
lkclalso masks.12:49
lkclclass CROpFF5RM(FFPRRc0BaseRM, PredicateWidthBaseRM,12:49
lkcl                VLiBaseRM, DZBaseRM, SZBaseRM, CROpBaseRM):12:49
lkclthen12:49
lkcl    RC1: BaseRM[19] # cheat: set RC=1 based on ffirst mode being set12:49
lkcl    def specifiers(self, record):12:49
lkcl        yield from super().specifiers(record=record, mode="ff")12:49
lkclthat's probably needing to just be PredicateBaseRM now that i think about it12:50
lkclyep done12:51
lkclbotch-job-and-a-half in sv/trans/svp64.py sigh12:56
ghostmansd[m]> that's probably needing to just be PredicateBaseRM now that i think about it12:57
ghostmansd[m]Yeah quite likely12:57
lkclVLI mode added....12:58
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lkcloof ISACaller doesn't actually have support for sv.cmp *at all*.  whoops...15:00
markosghostmansd[m], don't want to bother you with this if it's too much trouble, I know time is pressing for other stuff as well16:24
markosfmvis/fishmv in binutils tha tis16:24
ghostmansd[m]That's OK, I'll remember to check it, but I can do it only tomorrow16:24
markosno problem16:25
markosthanks again16:25
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lkclfaaakinellfire fail-first is complicated on CR ops.18:42
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programmerjakelkcl: added stuff you mentioned to todo list in top comment: https://bugs.libre-soc.org/show_bug.cgi?id=817#c023:22
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