Thursday, 2022-10-20

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octaviusWhat does "edu" in maddedu stand for? The full name would be something like, Multiply-Add High/Low Doubleword Unsigned14:06
octaviusmaddhldu makes more sense (but I guess a mouthful14:07
lkclmultiply-add extended double unsigned14:13
octaviusJust figured it out XD14:14
lkclshould be in the title itself (because it goes into the Power ISA spec)14:14
octaviusIt wasn't in biginteger.mdwn14:14
octaviusfor the rfc, which version of the powerisa spec do we use, 3.0c or 3.1? In the bigint tex I see v3.0, but in rfc there appendices G and H which only occur in v3.114:27
octaviusAh, I guess v3.0 is mentioned because the madd instruction haven't changed since then14:29
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octaviusAdded first draft ls003, text copied from biginteger.mdwn (svp64 removed). Need to update the opcode allocation (unless EXT04 is still appropriate), as well check over. I'll look at the AV minmax instructions a bit later15:56
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lkclmoo-haa-haa, i got the inner loop of chacha20.16:41
lkclmarkos, it works - with suitable elwidth overrides, 32-bit add/xor/rotl32, 4 groups of 32 REMAP indices work perfectly16:44
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programmerjakefixed incorrect statement about maddld:;a=commitdiff;h=1d9fc37f6239bda658a779c3995606af8af8391f20:06
lkcloctavius, the language of the RFC needs to be more "x is added to y and placed into z"20:12
lkclthe wording of maddld (etc) can be used as a template20:12
lkclbtw we need a bugreport for it20:13
lkcl is for ls00220:13
lkclso, maddhd says:20:14
lkcl"The 64-bit operands are (RA), (RB), and (RC). The20:14
lkcl128-bit product of the operands (RA) and (RB) is20:14
lkcladded to (RC). The high-order 64 bits of the 128-bit20:14
lkclsum are placed into register RT.20:14
lkcltherefore, we literally cut-and-paste that text20:14
lkcl"The low-order 64-bits of the 128-bit sum are placed into register RC"20:15
lkclalso, you removed the tag20:17
lkclwhich ensures that ls003 is missing from this auto-generated page:
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