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| programmerjake | cesar: you have mail delivery turned off for libre-soc-isa, that's likely caused by libre-soc.org not sending to gmail correctly over the last week (now fixed, thanks alain!): | 01:11 |
|---|---|---|
| programmerjake | https://lists.libre-soc.org/mailman/listinfo/libre-soc-isa | 01:11 |
| programmerjake | you'll want to re-enable mail delivery if you didn't intentionally disable it | 01:14 |
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| lkcl | markos, you removed the payments from #229. https://bugs.libre-soc.org/show_activity.cgi?id=229 | 10:59 |
| markos | ? | 10:59 |
| markos | when did I do that | 11:00 |
| lkcl | konstantinos@vectorcamp.gr2022-10-14 11:44:09 BST | 11:00 |
| markos | I think I might have added a comment and didn't refresh the page when I did | 11:00 |
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| markos | no i didn't add anything | 11:01 |
| markos | I have no idea how this happened | 11:01 |
| lkcl | and you got a warning, "your changes may overwrite other edits"? | 11:01 |
| lkcl | and you went, "yeah i can ignore that"? | 11:01 |
| markos | right | 11:01 |
| markos | apologies | 11:01 |
| markos | yeah I added a comment | 11:02 |
| lkcl | now you know, you can't ignore the warnings :) | 11:02 |
| markos | I probably clicked so fast I missed the warning | 11:02 |
| lkcl | particularly as that's for financial Auditing (EU Compliance for NLnet) | 11:03 |
| markos | I'll be more careful next time :D | 11:03 |
| lkcl | fortunately the history contains what was in it so i've restored it | 11:03 |
| markos | thanks and again sorry | 11:03 |
| lkcl | (and also updated the payment date information for you) | 11:03 |
| lkcl | can you check that you've received the money? (14th and 20th) | 11:03 |
| markos | yes, all good | 11:04 |
| lkcl | brilliant | 11:04 |
| markos | same day deposits even | 11:04 |
| lkcl | yehyeh. zero charges to NLnet as it's EU bank transfers | 11:05 |
| lkcl | ahh now i have the fun task of reconciling 5 remaining grants that ended mid-october | 11:06 |
| lkcl | removing all outstanding payments urrrr | 11:06 |
| lkcl | ghostmansd[m], "Is Rc used to indicate the two modes?" | 11:19 |
| lkcl | no | 11:19 |
| lkcl | Rc=1 is a post-analysis phase | 11:19 |
| lkcl | there's no "&" operator in Power ISA notation (there is, it's a logical-and, not bitwise-and). get the bits directly | 11:21 |
| lkcl | n <- (RB)[XLEN/2:XLEN-1] # Limit RB to upper word (32-bits) | 11:21 |
| lkcl | also bear in mind, the Power ISA spec - and the whole reason why SelectableInt exists - is extreme-strict about bitlength | 11:22 |
| lkcl | (unlike programming languages which don't give a shit, with the possible exception of ADA) | 11:23 |
| programmerjake | and rust...it intentionally has no silent conversions between integer types, you need to explicitly convert. | 12:05 |
| programmerjake | actually, & in pseudocode notation is bitwise and: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/fixedlogical.mdwn;h=28311ce33583aec9a3eba5c5bdf20304b1fea263;hb=753ba7273a910ba697173d58ea998f7730e6849d#l21 | 12:06 |
| programmerjake | powerisa just calls that logical and, it's still bitwise though, not c && or python `and` | 12:07 |
| programmerjake | have a safe family trip, luke! | 12:11 |
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| lkcl | programmerjake, appreciated. got a "new" car, 1988 peugeot 205 1.8 diesel, 60mpg (!) for it | 12:40 |
| octavius | Oh wow! | 12:41 |
| lkcl | (the other one, the brake pads are shot, clutch is going: brake replacement == GBP 300, clutch replacement == GBP 350+, which is 50% the value of the 35-year-old peugeot 205) | 12:41 |
| octavius | You going away for the day? | 12:41 |
| lkcl | week | 12:42 |
| octavius | very nice | 12:42 |
| lkcl | liverpool museum. doctor who exhibition | 12:42 |
| lkcl | last week, but outside of school half-term. they extended it to nov 6th | 12:42 |
| octavius | Are you going straight there, or stopping somewhere in the middle? | 12:43 |
| lkcl | stopping at least twice | 12:43 |
| lkcl | in a 35-year-old vehicle i really don't want to go over 65 mph, which means it'll be.... at least 4 hours | 12:44 |
| octavius | Indeed | 12:45 |
| lkcl | i'm taking the laptop (etc.) and probably the UPS :) and the WIFI 4G router... | 12:46 |
| lkcl | i just won't be online all the time | 12:46 |
| octavius | Sure, but do try to spend time with the family :) | 12:48 |
| octavius | Also, I'll soon be getting one of those smarty sim's, and testing it out with a USB modem and openwrt router | 12:49 |
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| lkcl | let me put you in touch with marie, we get 20 quid for an introduction | 13:05 |
| octavius | Hopefully your link will work (as I've registered already) | 13:30 |
| lkcl | octavius, oh doh | 13:32 |
| lkcl | octavius, can you avoid inserting tabs into pages (ls003 pseudocode has been converted to tabs) | 13:37 |
| octavius | Sorry, not sure how that happened, I'll check better next commit | 13:37 |
| lkcl | if you're using vim you can set up a ~/.vimrc | 13:39 |
| lkcl | syntax on | 13:40 |
| lkcl | set ts=4 | 13:40 |
| lkcl | set sw=4 | 13:40 |
| lkcl | set expandtab | 13:40 |
| lkcl | expandtab's the "important" one | 13:40 |
| octavius | Thanks, will do | 13:44 |
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| lkcl | ghostmansd, looks great. | 18:27 |
| lkcl | it is possible to do this: | 18:27 |
| ghostmansd | not yet, there's some fuckup with sm operand | 18:27 |
| lkcl | case (0): sum[0:XLEN-1] <- (((RB) || 0b0) + (RA)) | 18:28 |
| ghostmansd | its range is being considered to be 3 | 18:28 |
| lkcl | you have + switch (sh) | 18:28 |
| lkcl | not "switch (sm)" | 18:28 |
| lkcl | definitely should not be the case | 18:28 |
| lkcl | dsld uses a switch (sm) and it works perfectly fine | 18:29 |
| ghostmansd | switch (sh) | 18:29 |
| ghostmansd | Ah yes, 1 sec | 18:29 |
| lkcl | several unit tests confirm that a switch(sm) works perfectly | 18:29 |
| ghostmansd | no the issue is not in the switch | 18:29 |
| lkcl | also you want the same as what i did as a throwaway comment yesterday | 18:29 |
| ghostmansd | hang on | 18:29 |
| lkcl | n | 0b0 will be 65 bits | 18:30 |
| lkcl | (RB) || 0b0 will be 65 bits sorry | 18:30 |
| lkcl | (B) || 0b00 will be 66 bits | 18:30 |
| lkcl | and like i said this morning, and as you know from using SelectableInt(), a 66-bit thing {any-operator-with} a 64-bit thing is guaranteed to be an error | 18:31 |
| ghostmansd | OK fixed sm | 18:31 |
| ghostmansd | next, to bit count | 18:31 |
| lkcl | https://libre-soc.org/irclog/%23libre-soc.2022-10-24.log.html#t2022-10-24T21:11:15 | 18:32 |
| ghostmansd | do you want [0:XLEN-1] on the other side? | 18:32 |
| lkcl | case (0): RT <- ((RB)[0:XLEN-2] || [0]) + (RA) | 18:32 |
| ghostmansd | sum[0:XLEN-1] <- (((RB) || 0b0) + (RA))[0:XLEN-1] | 18:32 |
| lkcl | case (1): RT <- ((RB)[0:XLEN-3] || [0]*2) + (RA) | 18:32 |
| ghostmansd | Ah, so we discard the last bit | 18:32 |
| ghostmansd | Right, that I forgot | 18:32 |
| lkcl | yes. it's essential. | 18:33 |
| lkcl | pain-in-the-ass, but essential. | 18:33 |
| lkcl | it's so that there's no possibility of ambiguity in the spec | 18:33 |
| ghostmansd | sum[0:XLEN-1] <- (((RB)[XLEN-4-1] || 0b0000) + (RA)) | 18:33 |
| ghostmansd | same for n | 18:33 |
| lkcl | sum[0:XLEN-1] <- (((RB)[XLEN-4:XLEN-1] || 0b0000) + (RA)) | 18:33 |
| lkcl | (RB)[XLEN-4-1] is of length 1 bit | 18:34 |
| ghostmansd | Ah yes | 18:34 |
| lkcl | for shadduw you have to set up n <- [0]*(XLEN/2) || (RB)[XLEN/2:XLEN-1] | 18:34 |
| lkcl | to make it 64-bit | 18:35 |
| lkcl | *then* you can do the add-with-shift part | 18:35 |
| ghostmansd | OK should be better now | 18:37 |
| ghostmansd | ah wait | 18:37 |
| ghostmansd | no, from 0 | 18:37 |
| ghostmansd | sigh | 18:37 |
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| ghostmansd | sum[0:XLEN-1] <- (((RB)[XLEN-4:XLEN-1] || 0b0000) + (RA)) | 18:42 |
| ghostmansd | Shouldn't this also start with 0 for RB? | 18:42 |
| ghostmansd | please check the recent version | 18:42 |
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| ghostmansd | OK I found the issue what's wrong when building the basic opcode for shadd/shadduw | 19:06 |
| ghostmansd | sm overlaps with XO | 19:06 |
| ghostmansd | bit 21 | 19:06 |
| ghostmansd | Yeah solved this | 19:11 |
| ghostmansd | for the record, this happens in the current code I have, perhaps not present on master | 19:12 |
| ghostmansd | anyway, these changes are not related | 19:12 |
| ghostmansd | will be pushed separately | 19:12 |
| lkcl | yes, that's deliberate. it should be overlapping with 21 and 22. | 19:44 |
| lkcl | remember "--11101110-,ALU,OP_SHADD,RA"? | 19:44 |
| lkcl | the discussion yesterday? | 19:44 |
| lkcl | ghostmansd, https://libre-soc.org/irclog/%23libre-soc.2022-10-24.log.html#t2022-10-24T21:01:52 | 19:45 |
| lkcl | rebased, all good | 19:47 |
| lkcl | there's nothng "wrong"... oh except it might "appear" to be "wrong" in the Z23 function, you need the bottom 2 bits of the XO to be zero | 19:49 |
| lkcl | ... | 19:49 |
| lkcl | --01101110-,ALU,OP_SHADD,RA, | 19:49 |
| lkcl | _insn("shadd", PO=22, XO=0b01101110, Rc=0), | 19:49 |
| lkcl | those are effectively completely different XOs | 19:49 |
| lkcl | the "XO-from-the-csv-file" where the bit-pattern-start-and-end are defined in insndb.csv | 19:50 |
| lkcl | (as 21-31) | 19:50 |
| lkcl | the *manual* re-creation of Z23() it specifies bits 23-30, rather than picking up XO from the CSV file (as it will do in the future) | 19:51 |
| lkcl | but that's for bug... ermermermerm... 950 to solve | 19:52 |
| lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=950 | 19:52 |
| lkcl | the overlap - the fact that csv-files can have an XO which is *not* strictly part of the spec - is something that'll have to be dealt with somehow | 19:53 |
| lkcl | but | 19:53 |
| lkcl | there's nothing "wrong" with what you've done, it's perfect. | 19:53 |
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| lkcl | next thing, some unit tests. those go under... https://bugs.libre-soc.org/show_bug.cgi?id=967 | 20:01 |
| ghostmansd[m] | Yep | 20:02 |
| ghostmansd[m] | Will do these soon | 20:02 |
| ghostmansd[m] | This _custom_insn stuff will be dropped soon, added to keep in sync with master | 20:03 |
| lkcl | ack. just putting links into bugreport | 20:03 |
| lkcl | yehyeh | 20:03 |
| ghostmansd[m] | But perhaps my local branch will work even without these | 20:03 |
| ghostmansd[m] | Didn't have time to check it now, since that branch must be rebased | 20:03 |
| ghostmansd[m] | And the tasks which depend on this branch are put on hold anyway | 20:04 |
| octavius | lkcl, I saw you changed "[0]*64" to "EXTZ()" in divmod2du (fair enough, I forgot that's what's used in the PowerISA spec), | 20:08 |
| octavius | however should "[0]*64" in the "if" statement be changed to "0"? | 20:08 |
| lkcl | yes i put it back to what it was | 20:08 |
| octavius | Ah, is the [0]*64 syntax acceptable? | 20:09 |
| lkcl | you mean "if ((RA) <u (RB)) & ((RB) != [0]*64) then" ? | 20:09 |
| lkcl | well, have a look at the original | 20:09 |
| lkcl | https://libre-soc.org/openpower/isa/svfixedarith/ | 20:09 |
| lkcl | which has unit tests. | 20:09 |
| lkcl | which work 100%. | 20:10 |
| octavius | I just thought [x]*y was a Python syntax | 20:11 |
| octavius | Didn't see it in the PowerISA spec | 20:11 |
| lkcl | it's a subscript notation in Power ISA | 20:11 |
| lkcl | which we can't obviously do in ASCII | 20:11 |
| octavius | Ah....makes sense! | 20:11 |
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| ghostmansd | lkcl, before unit tests, I'll provide binutils support | 20:36 |
| ghostmansd | I'll do it in scope of 966, it'd be annoying to have the fourth task | 20:38 |
| ghostmansd | binutils support turned out to be easier than I expected | 21:06 |
| ghostmansd | Done | 21:11 |
| octavius | Ah, || is concatinate... that makes a lot more sense :D | 21:28 |
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