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| octavius | do we have any svp64 nmigen code yet? Was just wondering if we start doing any implementation yet (other than the simulator) | 12:02 |
|---|---|---|
| octavius | for example to run some svp64 assembly in verilator/ghdl (or fpga) | 12:05 |
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| lkcl | octavius, yes of course. implemented over 18 months ago. | 13:26 |
| lkcl | includes support for twin predicates. | 13:28 |
| lkcl | no elwidth overrides, none of the advanced modes | 13:28 |
| octavius | Nice, I gotta try getting something to run on an fpga then | 14:33 |
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| lkcl | octavius, you got an orangecrab, right? https://libre-soc.org/HDL_workflow/orangecrab/ | 15:15 |
| octavius | Yes, just got distracted with verilator a few weeks ago (although the orangecrab has been sitting for a while...) | 15:37 |
| octavius | Tried compiling nextpnr-ecp5, getting an assertion failure, did you get this before? | 15:42 |
| octavius | python3: /home/rohdo/src/nextpnr/prjtrellis/libtrellis/src/DedupChipdb.cpp:116: std::shared_ptr<Trellis::DDChipDb::DedupChipdb> Trellis::DDChipDb::make_dedup_chipdb(Trellis::Chip&, bool, bool): Assertion `rw.belsUphill.size() <= 1' failed. | 15:42 |
| octavius | nextpnr git commit is e069b3bc | 15:43 |
| octavius | Is the openpower meeting cancelled today? | 16:51 |
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| abhi | Hi | 17:45 |
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