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| Guest60 | hi | 06:06 |
|---|---|---|
| Guest60 | all of you | 06:06 |
| klys | hello | 06:19 |
| programmerjake | hi | 06:21 |
| Guest60 | hlo jake | 06:22 |
| Guest60 | are you currently contributing | 06:23 |
| klys | he is | 06:23 |
| Guest60 | hi klys | 06:26 |
| Guest60 | what are you doing | 06:26 |
| klys | i'm downloading verilator for this laptop | 06:26 |
| Guest60 | for why | 06:27 |
| klys | since I want to learn some basic verilog | 06:27 |
| Guest60 | that's nice | 06:48 |
| Guest60 | klys please check your inbox | 06:48 |
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| *** Guest6085 is now known as bagiyal | 06:52 | |
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| klys | how does this look, and is there a way to recreate it in nmigen: http://45.55.20.239/verilog/jkff.v.txt | 07:46 |
| klys | rather | 07:46 |
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| klys | how does this look, and is there a way to recreate it in nmigen: http://show.ing.me/verilog/jkff.v.txt | 07:46 |
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| bagiyal | hi | 10:04 |
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| bagiyal | :-( | 10:11 |
| programmerjake | hi | 10:13 |
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| lkcl | klys, oh allo, been a while! | 11:31 |
| lkcl | i got disconnected and reconnected, just saw this https://libre-soc.org/irclog/%23libre-soc.2022-12-15.log.html | 11:32 |
| lkcl | answer: yes, of course - you just simply use a nmigen switch/case statement | 11:32 |
| lkcl | and rather than "if ck()" you use "sync +=" inside the case statement | 11:33 |
| lkcl | off-the-cuff... erm...ermermem... | 11:33 |
| lkcl | from nmigen import Module, Elaboratable, Signal (etc. etc.) | 11:33 |
| lkcl | class jkk: | 11:34 |
| lkcl | def elaborate(self, platform): | 11:34 |
| lkcl | m = Module() | 11:34 |
| lkcl | sync = m.d.sync | 11:34 |
| lkcl | with m.Switch(Cat(self.J, self.K)): | 11:35 |
| lkcl | with m.Case(0b10): | 11:35 |
| lkcl | sync += self.Qi.eq(1) | 11:35 |
| lkcl | etc. etc. you get the general idea | 11:36 |
| lkcl | the __init__() of class jkk would be: | 11:36 |
| lkcl | def __init__(self, Q, J, K): | 11:36 |
| lkcl | self.Qi = self.Q = Q | 11:37 |
| lkcl | self.J, self.K = J, K | 11:37 |
| lkcl | i made self.Qi == Self.Q because i slightly messed up above, it should have been "sync += self.Q.eq(1)" | 11:37 |
| lkcl | don't bother assigning to a temporary "reg" - nmigen will auto-create the "temporary" when you use sync += by going "oh, sync is a ck-controlled domain, let me create a temporary Q$next for you before kindly assigning that auto-created Signal to the DFF named Q for you again all automatically so that you don't have to piss about" | 11:39 |
| * lkcl thinks | 11:40 | |
| lkcl | looking more closely, you *might* have to create a neg-edge domain | 11:41 |
| sadoon[m] | Turns out the only two Xilinx boards I have are Zynq (which is great because of the SoC, not great because support hasn't matured on those afaict) | 12:02 |
| sadoon[m] | I know I saw mention of a specific board on libre-soc.org but I can't seem to find it again | 12:03 |
| sadoon[m] | I remember one being used by the project and supported by nmigen, is it the arty 7000? | 12:06 |
| sadoon[m] | I'm thinking of also getting a ulx3s since it's supported by so many projects but the 85k LUT version is on backorder :( | 12:09 |
| sadoon[m] | Aha, on hdl_workflow it says arty a7 100t board, awesome | 12:09 |
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| klys | lkcl, thanks a lot, looking forward to trying it out | 13:48 |
| klys | looks like I'll have to figure out how to clone nmigen from git.libre-soc.org first | 14:03 |
| klys | following instructions from https://web.archive.org/web/20211208074340/http://nmigen.info/nmigen/latest/install.html | 14:03 |
| klys | in any case, I have to leave for work soon this morning. | 14:03 |
| klys | should be back in ~nine hours | 14:07 |
| programmerjake | clone it from https://gitlab.com/nmigen/nmigen.git, not git.libre-soc.org, the libre-soc repo is out of date and not really used anymore | 14:19 |
| klys | ...on the bus at the moment. i have a command now called nmigen-rpc | 14:50 |
| klys | later! good luck with libre-soc! | 15:02 |
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| octavius | lkcl, do you remember how long microwatt-verilator of dtbImage.microwatt took for you to to the login prompt? | 15:33 |
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| klys | hello | 23:26 |
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