Thursday, 2022-12-15

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Guest60all of you06:06
Guest60hlo jake06:22
Guest60are you currently contributing06:23
klyshe is06:23
Guest60hi klys06:26
Guest60what are you doing06:26
klysi'm downloading verilator for this laptop06:26
Guest60for why06:27
klyssince I want to learn some basic verilog06:27
Guest60that's nice06:48
Guest60klys please check your inbox06:48
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klyshow does this look, and is there a way to recreate it in nmigen:
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klyshow does this look, and is there a way to recreate it in nmigen:
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lkclklys, oh allo, been a while!11:31
lkcli got disconnected and reconnected, just saw this
lkclanswer: yes, of course - you just simply use a nmigen switch/case statement11:32
lkcland rather than "if ck()" you use "sync +=" inside the case statement11:33
lkcloff-the-cuff... erm...ermermem...11:33
lkclfrom nmigen import Module, Elaboratable, Signal (etc. etc.)11:33
lkclclass jkk:11:34
lkcl   def elaborate(self, platform):11:34
lkcl      m = Module()11:34
lkcl       sync = m.d.sync11:34
lkcl    with m.Switch(Cat(self.J, self.K)):11:35
lkcl        with m.Case(0b10):11:35
lkcl          sync += self.Qi.eq(1)11:35
lkcletc. etc. you get the general idea11:36
lkclthe __init__() of class jkk would be:11:36
lkcl    def __init__(self, Q, J, K):11:36
lkcl        self.Qi = self.Q = Q11:37
lkcl      self.J, self.K = J, K11:37
lkcli made self.Qi == Self.Q because i slightly messed up above, it should have been "sync += self.Q.eq(1)"11:37
lkcldon't bother assigning to a temporary "reg" - nmigen will auto-create the "temporary" when you use sync += by going "oh, sync is a ck-controlled domain, let me create a temporary Q$next for you before kindly assigning that auto-created Signal to the DFF named Q for you again all automatically so that you don't have to piss about"11:39
* lkcl thinks11:40
lkcllooking more closely, you *might* have to create a neg-edge domain11:41
sadoon[m]Turns out the only two Xilinx boards I have are Zynq (which is great because of the SoC, not great because support hasn't matured on those afaict)12:02
sadoon[m]I know I saw mention of a specific board on but I can't seem to find it again12:03
sadoon[m]I remember one being used by the project and supported by nmigen, is it the arty 7000?12:06
sadoon[m]I'm thinking of also getting a ulx3s since it's supported by so many projects but the 85k LUT version is on backorder :(12:09
sadoon[m]Aha, on hdl_workflow it says arty a7 100t board, awesome12:09
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klyslkcl, thanks a lot, looking forward to trying it out13:48
klyslooks like I'll have to figure out how to clone nmigen from first14:03
klysfollowing instructions from
klysin any case, I have to leave for work soon this morning.14:03
klysshould be back in ~nine hours14:07
programmerjakeclone it from, not, the libre-soc repo is out of date and not really used anymore14:19
klys...on the bus at the moment.  i have a command now called nmigen-rpc14:50
klyslater!  good luck with libre-soc!15:02
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octaviuslkcl, do you remember how long microwatt-verilator of dtbImage.microwatt took for you to to the login prompt?15:33
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