| klys | perhaps there is a better place to discuss it, here I am so far: http://show.ing.me/verilog/jkff-15dec2022.py.txt | 00:24 |
|---|---|---|
| klys | yea http://show.ing.me/verilog/jkff-0001-15dec2022.py.txt | 02:58 |
| lkcl | klys, you may have better luck converting a verilog model of a jkff that was written not from a... a... "simulator style module from a standard cell library or FPGA model" | 03:41 |
| lkcl | one that has "@posedge(clk)" and/or "@negedge(clk)" in it | 03:41 |
| lkcl | i had to think through the implications of "if ck == 1 ... else..." in terms of "what happens just at the point when rising from 0 to 1 and back again" | 03:42 |
| klys | yea http://show.ing.me/verilog/jkff-0002-15dec2022.py.txt | 03:43 |
| lkcl | and i *think* it's just "@posedge(clk)", the normal way stuff is written | 03:43 |
| lkcl | with m.Switch(pos.clk): | 03:43 |
| lkcl | with m.Case(0): | 03:43 |
| lkcl | you can't do that | 03:43 |
| lkcl | delete it | 03:44 |
| klys | k | 03:44 |
| lkcl | go back to http://45.55.20.239/verilog/jkff-0001-15dec2022.py.txt | 03:44 |
| lkcl | you wanted: | 03:44 |
| lkcl | neg += self.Q.eq(...) | 03:44 |
| lkcl | or | 03:44 |
| lkcl | pos += self.Q.eq(....) | 03:45 |
| lkcl | but | 03:45 |
| klys | read some of that here: https://github.com/RobertBaruch/nmigen-tutorial/blob/master/3_modules.md | 03:45 |
| lkcl | pos is declared *as the same thing* as what "m.d.sync" already is | 03:45 |
| lkcl | so you didn't need to create it, strictly speaking | 03:45 |
| lkcl | you're very rapidly getting into some of the advanced areas of nmigen by creating your own ClockDomains | 03:46 |
| lkcl | and they're a bit of a pain to both set up and also simulate | 03:46 |
| lkcl | best to stick with sync | 03:46 |
| klys | k | 03:46 |
| klys | look at __init__ a bit, I think J and K should be Signal(...) ? | 03:47 |
| lkcl | by default/convention __init__ is the first function | 03:47 |
| klys | that way I can use them as ports | 03:48 |
| lkcl | that entirely depends on what style *you* want to follow, not on anything else | 03:48 |
| lkcl | but... no i don't recommend you do what you've done. | 03:48 |
| lkcl | go back to what i suggested | 03:48 |
| klys | well I did what you suggested just this line is what I'm talking about: self.J, self.K = J, K | 03:49 |
| lkcl | then - by convention - initialise J and K as Signals with the required reset value from the prerequisite source... *OUTSIDE* of the class instance | 03:49 |
| klys | so I'm working with 0001 for now | 03:49 |
| lkcl | this is purely a coding convention that you are entirely free and clear to completely ignore | 03:50 |
| lkcl | it is not a requirement of python | 03:50 |
| lkcl | it is not a requirement of nmigen | 03:50 |
| lkcl | you are free and clear to choose to ignore my advice and make your own conventions | 03:50 |
| klys | I guess if you want it to wire to another module you need to expose it as a port? | 03:50 |
| klys | a port is like a wire? | 03:50 |
| lkcl | ports() the function is another convention | 03:51 |
| lkcl | but ports *of the module* have to be auto-detected by nmigen, during construction and connection to other modules | 03:51 |
| lkcl | by the time you get to the absolute top level, that's really the only point that you should be explicitly declaring a list of ports to tell (ultimately yosys) what you want as the inputs/outputs | 03:52 |
| klys | it returns an array and with your advice I was getting an error passing [self.J, self.K] because of the ports() call at the bottom of version 0002 | 03:52 |
| lkcl | if you fail to specify them, nmigen will try to work them out for you | 03:53 |
| lkcl | ssut = jkk( 0, 1 ) | 03:53 |
| klys | this one: raise TypeError("Object {!r} is not an nMigen signal".format(signal)) | 03:54 |
| lkcl | ah ok you're passing in integer values as initialisation parameters, ok | 03:54 |
| lkcl | that's because you had passed a list-of-a-list | 03:54 |
| lkcl | or, a list-of-a-tuple | 03:54 |
| lkcl | you can only pass a list of Signals as traces | 03:55 |
| lkcl | you had attempted to pass something like | 03:55 |
| lkcl | [Signal(), (Signal(), Signal())] | 03:55 |
| lkcl | which you could have found | 03:55 |
| lkcl | by *printing* ssut.ports() | 03:55 |
| lkcl | print(ssut.ports()) | 03:56 |
| lkcl | and seeing that it was not a list of Signals() | 03:56 |
| lkcl | you did not need to ask me for that advice :) | 03:56 |
| klys | yea http://show.ing.me/verilog/jkff-0003-15dec2022.py.txt | 03:56 |
| klys | which has the above error | 03:56 |
| lkcl | this should have been something that should have been your first instict | 03:56 |
| lkcl | instinct | 03:56 |
| lkcl | right, there you've made the mistake of setting self.J = 1 | 03:57 |
| lkcl | and self.K = 0 | 03:57 |
| lkcl | (or the other way round) | 03:57 |
| lkcl | ssut = jkk( 0, 1 ) | 03:57 |
| klys | and so those are integers | 03:57 |
| lkcl | def __init__(self, J, K): | 03:57 |
| lkcl | self.J, self.K = J, K | 03:57 |
| lkcl | yes. | 03:57 |
| lkcl | you wanted | 03:58 |
| lkcl | J = Signal(1, reset=0) | 03:58 |
| lkcl | K = Signal(1, reset=1) | 03:58 |
| lkcl | ssut = jkk(J, K) | 03:58 |
| lkcl | .... | 03:58 |
| lkcl | ... | 03:58 |
| lkcl | .. | 03:58 |
| klys | oh I see then | 03:58 |
| lkcl | and then self.J, self.K would equal the Signals() you initialised *outside* the module | 03:58 |
| lkcl | (as i wrote above, scroll back, look for word "convention") | 03:59 |
| lkcl | but again | 03:59 |
| lkcl | you could have found this with "print(ssut.ports())" | 03:59 |
| lkcl | and gone "errr" :) | 03:59 |
| klys | and saw that they were integers, I knew, I just wasn't aware this was a problem | 03:59 |
| lkcl | you can do prints() all over the place with nmigen because you don't care at all about the stdout/stderr | 04:00 |
| lkcl | neither of those get "into" the verilog output | 04:00 |
| lkcl | nor the simulation output | 04:00 |
| lkcl | this is just standard python debugging tools/techniques at this point | 04:00 |
| klys | so right I may need to create a neg-edge domain, and you suggest doing this outside the class | 04:01 |
| lkcl | and "print()" is one of the fastest, simplest and most ubiquitous hackiest ways to get internal information :) | 04:01 |
| lkcl | mmm... i haven't used them often enough to say with confidence how you should use them | 04:01 |
| lkcl | but if you look at c4m-jtag you'll see a really good use of them | 04:02 |
| lkcl | 1 sec | 04:02 |
| klys | [(sig Q), (sig J), (sig K)] | 04:02 |
| lkcl | that looks perfectly fine | 04:02 |
| lkcl | https://git.libre-soc.org/?p=c4m-jtag.git;a=blob;f=c4m/nmigen/jtag/tap.py;hb=HEAD | 04:02 |
| lkcl | if you can get this working as a first experiment without complicating your life by also tackling negedge ClockDomains that would also make my life a little easier | 04:03 |
| klys | :) | 04:03 |
| lkcl | esp given it's 4am in the UK at the moment | 04:03 |
| klys | tomorrow's my day off | 04:03 |
| lkcl | study that file and how it's used in soc | 04:04 |
| lkcl | ok i leave you to re-read the early parts of the chat again, middle of the night here. | 04:05 |
| lkcl | till tomorrow | 04:05 |
| klys | thanks lkcl | 04:05 |
| klys | good night. | 04:06 |
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| bagiyal | hi | 15:44 |
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| bagiyal | all of you guys | 15:45 |
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| octavius | hi bagiyal, are you new here? Haven't seen you before | 16:36 |
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| octavius | apologies for the silence, most people probably busy atm | 16:36 |
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| lkcl | does someone know how libera matrix works? | 17:47 |
| lkcl | to xplain to bagiyal | 17:47 |
| lkcl | thx | 17:47 |
| bagiyal | yes help me | 18:05 |
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| cesar | Hi bagiyal, to open this room on Matrix, try this link: https://matrix.to/#/#libre-soc:libera.chat | 20:26 |
| lkcl | cesar, magic, i'll pass that on. he's struggling with india internet | 20:27 |
| lkcl | and he's on GMT+3.5 so it's v. late for him now | 20:27 |
| lkcl | https://video.ibm.com/recorded/132378135 | 20:37 |
| klys | yea http://show.ing.me/verilog/jkff-0004-15dec2022.py.txt | 21:03 |
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