Friday, 2022-12-16

klysperhaps there is a better place to discuss it, here I am so far:
lkclklys, you may have better luck converting a verilog model of a jkff that was written not from a... a... "simulator style module from a standard cell library or FPGA model"03:41
lkclone that has "@posedge(clk)" and/or "@negedge(clk)" in it03:41
lkcli had to think through the implications of "if ck == 1 ... else..." in terms of "what happens just at the point when rising from 0 to 1 and back again"03:42
lkcland i *think* it's just "@posedge(clk)", the normal way stuff is written03:43
lkcl      with m.Switch(pos.clk):03:43
lkcl         with m.Case(0):03:43
lkclyou can't do that03:43
lkcldelete it03:44
lkclgo back to
lkclyou wanted:03:44
lkclneg += self.Q.eq(...)03:44
lkclpos += self.Q.eq(....)03:45
klysread some of that here:
lkclpos is declared *as the same thing* as what "m.d.sync" already is03:45
lkclso you didn't need to create it, strictly speaking03:45
lkclyou're very rapidly getting into some of the advanced areas of nmigen by creating your own ClockDomains03:46
lkcland they're a bit of a pain to both set up and also simulate03:46
lkclbest to stick with sync03:46
klyslook at __init__ a bit, I think J and K should be Signal(...) ?03:47
lkclby default/convention __init__ is the first function03:47
klysthat way I can use them as ports03:48
lkclthat entirely depends on what style *you* want to follow, not on anything else03:48
lkclbut... no i don't recommend you do what you've done.03:48
lkclgo back to what i suggested03:48
klyswell I did what you suggested just this line is what I'm talking about: self.J, self.K = J, K03:49
lkclthen - by convention - initialise J and K as Signals with the required reset value from the prerequisite source... *OUTSIDE* of the class instance03:49
klysso I'm working with 0001 for now03:49
lkclthis is purely a coding convention that you are entirely free and clear to completely ignore03:50
lkclit is not a requirement of python03:50
lkclit is not a requirement of nmigen03:50
lkclyou are free and clear to choose to ignore my advice and make your own conventions03:50
klysI guess if you want it to wire to another module you need to expose it as a port?03:50
klysa port is like a wire?03:50
lkclports() the function is another convention03:51
lkclbut ports *of the module* have to be auto-detected by nmigen, during construction and connection to other modules03:51
lkclby the time you get to the absolute top level, that's really the only point that you should be explicitly declaring a list of ports to tell (ultimately yosys) what you want as the inputs/outputs03:52
klysit returns an array and with your advice I was getting an error passing [self.J, self.K] because of the ports() call at the bottom of version 000203:52
lkclif you fail to specify them, nmigen will try to work them out for you03:53
lkclssut = jkk( 0, 1 )03:53
klysthis one: raise TypeError("Object {!r} is not an nMigen signal".format(signal))03:54
lkclah ok you're passing in integer values as initialisation parameters, ok03:54
lkclthat's because you had passed a list-of-a-list03:54
lkclor, a list-of-a-tuple03:54
lkclyou can only pass a list of Signals as traces03:55
lkclyou had attempted to pass something like03:55
lkcl[Signal(), (Signal(), Signal())]03:55
lkclwhich you could have found03:55
lkclby *printing* ssut.ports()03:55
lkcland seeing that it was not a list of Signals()03:56
lkclyou did not need to ask me for that advice :)03:56
klyswhich has the above error03:56
lkclthis should have been something that should have been your first instict03:56
lkclright, there you've made the mistake of setting self.J = 103:57
lkcland self.K = 003:57
lkcl(or the other way round)03:57
lkclssut = jkk( 0, 1 )03:57
klysand so those are integers03:57
lkcl   def __init__(self, J, K):03:57
lkcl      self.J, self.K = J, K03:57
lkclyou wanted03:58
lkclJ = Signal(1, reset=0)03:58
lkclK = Signal(1, reset=1)03:58
lkclssut = jkk(J, K)03:58
klysoh I see then03:58
lkcland then self.J, self.K would equal the Signals() you initialised *outside* the module03:58
lkcl(as i wrote above, scroll back, look for word "convention")03:59
lkclbut again03:59
lkclyou could have found this with "print(ssut.ports())"03:59
lkcland gone "errr" :)03:59
klysand saw that they were integers, I knew, I just wasn't aware this was a problem03:59
lkclyou can do prints() all over the place with nmigen because you don't care at all about the stdout/stderr04:00
lkclneither of those get "into" the verilog output04:00
lkclnor the simulation output04:00
lkclthis is just standard python debugging tools/techniques at this point04:00
klysso right I may need to create a neg-edge domain, and you suggest doing this outside the class04:01
lkcland "print()" is one of the fastest, simplest and most ubiquitous hackiest ways to get internal information :)04:01
lkclmmm... i haven't used them often enough to say with confidence how you should use them04:01
lkclbut if you look at c4m-jtag you'll see a really good use of them04:02
lkcl1 sec04:02
klys[(sig Q), (sig J), (sig K)]04:02
lkclthat looks perfectly fine04:02
lkclif you can get this working as a first experiment without complicating your life by also tackling negedge ClockDomains that would also make my life a little easier04:03
lkclesp given it's 4am in the UK at the moment04:03
klystomorrow's my day off04:03
lkclstudy that file and how it's used in soc04:04
lkclok i leave you to re-read the early parts of the chat again, middle of the night here.04:05
lkcltill tomorrow04:05
klysthanks lkcl04:05
klysgood night.04:06
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bagiyalall of you guys15:45
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octaviushi bagiyal, are you new here? Haven't seen you before16:36
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octaviusapologies for the silence, most people probably busy atm16:36
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lkcldoes someone know how libera matrix works?17:47
lkclto xplain to bagiyal17:47
bagiyalyes help me18:05
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cesarHi bagiyal, to open this room on Matrix, try this link:
lkclcesar, magic, i'll pass that on. he's struggling with india internet20:27
lkcland he's on GMT+3.5 so it's v. late for him now20:27

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