Monday, 2022-12-19

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ghostmansdlkcl, regarding Rc and CSV18:10
ghostmansdThe only incorrect part in this change is Rc handling18:10
ghostmansdOther than that, it is perfectly logical.18:11
lkclhiya ghostmansd i've calmed down slightly18:11
lkcllogical yes, "Causes absolutely chaos" yes18:11
lkclthe way it works is:18:11
lkclthere isn't actually an Rc=1 instruction nor is there an OE=1 instruction in the Decoder18:11
lkcl(this comes from microwatt's decoder)18:12
lkclthere is only "add" for example18:12
ghostmansdYou have examples of specific Rc handling already in CSVs.18:12
ghostmansdWe're not the first.18:12
lkclthe microwatt decode1.vhdl contains a column that says "please also look at bit 30 and bit 31"18:12
ghostmansdaddic., andi., andis.18:12
lkclthis one is absolutely no different18:12
lkclby a *complete coincidence* these two instructions are using the "multi-mapping CSV" option18:13
ghostmansdHere's how I got at this issue18:13
ghostmansdSome context would be better18:13
lkclthe coincidence is deliberately being exploited but it is a coincidence18:13
ghostmansdI switched these into insndb, and found that I have dsld with two XOs: 52 and 53.18:14
lkclthe multi-mapping (multi-matching) of the PowerDecoder "switch/case" statements which happen to be allowed happens by a not-entirely-coincidence to match *exactly* with "Rc=0" and "Rc=1"18:14
lkclthat's correct.18:14
ghostmansdWhen we try to match the opcode, we have the list of possible XOs (like with isel).18:15
lkclthe "multi-mapping" we added a couple months back should create... yes.18:15
ghostmansdAnd the issue is that both dsld and dsld. match the instruction with Rc=1.18:15
lkcland be merged into one "pattern" (that weird algorithm Macbeth or something)18:15
lkclit is "as if" a binary pattern had been specified, "101100-"18:16
lkclwhere bit 31 - by a not-coincidence - matches with Rc=0/Rc=1.18:16
ghostmansdAnd, then, since dotted version is matched by either of these, it's only natural to keep these distinct.18:16
lkclby the time the matching occurs, it's now falling into exactly the same code-path as "addic/addic."18:17
lkclthe *entire* codepath to deal with Rc=1 would have to be changed in order to support the "natural and obvious" thing that you're suggesting is otherwise perfectly logical18:18
lkclunfortunately :)18:18
ghostmansdThat's why if it fails there, it must be specified the same way.18:18
lkclwait... hang on....18:18
lkcllet me take a look18:18
* lkcl oink18:19
lkclhow the hell did that end up there18:19
ghostmansdI should have provided this explanation yesterday, but after several hours of debugging into tests I was so fucking tired I couldn't.18:19
lkclmore to the point, how the hell did it actually *work*?? :)18:19
ghostmansdI don't know how it worked, but it is logical and natural.18:20
ghostmansdAgain: these differ only by Rc.18:20
lkclok leave it with me for a bit, i need to check it18:20
ghostmansdSince the mask incorporates Rc, the only way to circumvent it is to make Rc field to behave differently.18:20
lkclrc,lk,sgl pipe,comment,form,CONDITIONS18:20
ghostmansdI fucked up the exact Rc column, though.18:20
ghostmansdColumn 2118:21
lkclyep ok i'm with it now.18:21
ghostmansdThey differ by NONE/ONE18:21
ghostmansdThis is what I did wrong18:21
ghostmansdI specified NONE for both.18:21
lkclok so what's going on is that PowerDecoder has a "hard-coded-Rc-input-from-CSV" option18:21
lkclso it's going "i matched against 0b1100, Rc is hard-coded to zero"18:22
ghostmansdYes, exactly18:22
lkcl"i matched against 0b1101, Rc is hard-coded to one"18:22
lkclbleuch :)18:22
ghostmansdKinda circumventing the limitation in CSV18:22
ghostmansdHad we not grabbed Rc into pattern, we shouldn't had resorted to such tricks18:22
ghostmansdBut hey18:22
ghostmansdI'll push the updated version soon18:23
ghostmansdI'm really so fucking sick of tests18:23
lkclthat's something i hadn't even realised was being used. i knew it was there (i wrote and maintain PowerDecoder), but up until now i'd never paid attention to it18:23
lkcli know - but they're absolutely critical. without them we're royally screwed18:23
ghostmansdI'm slowly gnaw through disassembly tests18:23
ghostmansdYeah I know18:24
ghostmansdThere's no objections on this part :-)18:24
ghostmansdJust sharing the butthurt18:24
lkclok so... haha18:24
lkclcan i suggest doing the dsld/dsrd change as a separate commit? leave it till later if needed18:25
ghostmansdYes, it's separate18:26
ghostmansdI'm keeping this in branch yet18:26
ghostmansdOtherwise the repo ends up totally fucked18:26
ghostmansdWhen I started checking tests pretty everything was broken :-)18:26
ghostmansdMostly because of my desire to deal with it in one shot18:27
ghostmansdIt'd have been almost impossible to do it step-by-step, though, because the whole assembly is replaced18:27
ghostmansdThe next giant step would be to drop the tables for "mode" matching18:28
ghostmansdThis will be yet another pain in the ass, to be honest, because besides the major table we have we must also adopt all specifiers, too18:28
ghostmansde.g. "/sat" should also be able to check some file(s) to understand where it can be applied18:29
openpowerbot[mattermost] <lkcl> whoops transferring to mattermost, IRC gone borked18:29
ghostmansdI'm leaving this for latter18:29
openpowerbot[mattermost] <lkcl> it hasn't been implemented - at all18:29
openpowerbot[mattermost] <lkcl> /sat hasn't been implemented in ISACaller - at all.18:30
openpowerbot[mattermost] <lkcl> remember we're still in the process of implementing SVP6418:30
* lkcl pokes libera irc again18:34
lkclah ha, it's back18:35
ghostmansdWell there are many parts we haven't implemented yet properly, but these are in assembler already, and I shouldn't break existing tests for them. Even if all they check is assembly.18:50
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ghostmansdI would be very pissed if someone broke existing tests with the rationale "hey, but you know, it's not fully implemented anyway".18:51
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