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| lkcl | hooraay! | 08:09 |
|---|---|---|
| sadoon[m] | Awesome | 08:55 |
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| ghostmansd[m] | Hi folks, I'm thinking of taking another task. Options are: | 17:37 |
| ghostmansd[m] | 1. Update binutils with our assembler/disassembler (we currently lack some specifiers and similar stuff, mostly for branches and CR ops). | 17:37 |
| ghostmansd[m] | 2. Introduce something which allows us to deal with instruction aliases, both in our code and in binutils. This one I'm not sure how to start; do we have some section in ISA enumerating these? | 17:37 |
| ghostmansd[m] | Options/opinions? | 17:37 |
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| lkcl | 2 is inadviseable, i cannot say why yet. | 17:41 |
| lkcl | the reason will become clear at some point in the future | 17:42 |
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| lkcl | as in: information will become available that i am not at liberty to disclose | 17:43 |
| lkcl | that leaves (1) | 17:43 |
| lkcl | and (3) - cavatools. we need a c version of the python ISACaller pseudocode-to-python generator | 17:44 |
| lkcl | actually c++ because all operations will need to be overridden at some point in the future (for SVP64). i did this in the past with spike | 17:44 |
| ghostmansd[m] | Hm. I might take that one, since after I changed the job the FSF agreement is kinda in unclear state... | 17:44 |
| ghostmansd[m] | The 1) would be simpler, though, because I know what to do and know the scope. | 17:45 |
| lkcl | although i need to do the spec on cr-ops (and part of branches, and ld/st post-increment) | 17:47 |
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