programmerjake | @lkcl I realized fminmaxs[.] is redundant because fminmax produces the exact same results for f32-in-f64, imho we should remove it, what do you all think? for more details see https://bugs.libre-soc.org/show_bug.cgi?id=1057#c28 | 02:56 |
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programmerjake | so, lkcl, what do you think? should we remove fminmaxs? | 07:03 |
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programmerjake | got some inquiries about when we want to work on adding powerpc support to cranelift/wasmtime -- responded: https://github.com/bytecodealliance/wasmtime/issues/1183#issuecomment-1522865183 | 07:40 |
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ghostmansd[m] | Hi folks, FYI, I removed few remote branches on openpower-isa which were created by me. These were no longer actual. | 13:08 |
ghostmansd[m] | There are few more, perhaps we can drop these too. | 13:08 |
ghostmansd[m] | I consider branches which are 6 months old to be obsolete, to be honest, and don't see any value in keeping these. It'd be great if we could do a small cleanup. | 13:09 |
lkcl | programmerjake, yes good catch - wouldn't have occurred to me at all. i removed fminmaxs from ls012 optable.csv | 13:55 |
lkcl | ghostmansd[m], sensible. once merged i mean unless you intend to re-use a branch tag it really can go | 13:56 |
lkcl | programmerjake, another crucially-important flag is #ifdef MMA_EXTENSION | 13:57 |
lkcl | that is *not* a mandatory feature: like VSX it happens to be an optional feature that *IBM's* implementation, called "POWER10", chose to implement | 13:57 |
lkcl | powerpc64le-unknown-linux-gnu with the "-mpower10" target should enable mma and vsx by default | 13:58 |
lkcl | with the "-mpower9" target should enable vsx by default | 13:58 |
lkcl | > "Our processor is not far enough along to run Linux yet." | 14:00 |
lkcl | yes it is | 14:00 |
lkcl | also worth mentioning that IBM's A2I does not have VSX, nor A2O, and microwatt is v3.0 SFFS compliant, but the VSX support required 50% more FPGA resources for a *small* subset of VSX so they are not adding more | 14:03 |
lkcl | the EABI for SFFS basically drops back to version 1.4 https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.4.1.txt | 14:03 |
lkcl | and SVP64/SFFS EABI will simply add extra registers r32-127 fp32-127 cr8-127 to the existing ones. job done | 14:05 |
lkcl | > We will probably start working on the Cranelift backend in a few months, | 14:06 |
lkcl | don't whatever you do make committments like that without also having a full grant plan to back it up | 14:06 |
lkcl | the register allocation work you did should have had an *entire EUR 50,000 NLnet Grant* associated with it, just on its own | 14:07 |
lkcl | ghostmansd[m], found this | 14:20 |
lkcl | https://git.libre-soc.org/?p=binutils-gdb.git;a=blob;f=opcodes/ppc-opc.c;h=2db4f415413ea120483e817f0a8675f3aa3e6c8c;hb=5f4e0b013934af256dff12620886355a8aa3ab3d | 14:20 |
lkcl | 9433 {"fexp2s", XRC(59,908,0), X_MASK, SVP64, PPCVLE, {FRT, FRB}}, | 14:20 |
lkcl | SVP64 is a 64-bit prefixing system (actually, a 32-bit instruction saying "do-a-loop-on-the-next-instruction") | 14:21 |
lkcl | and it looks to me like the flag "SVP64" is being used with a different meaning | 14:21 |
lkcl | is that instruction "fexp2s" *really* intended to be *ONLY* accessible as a 64-bit prefixed instruction? | 14:21 |
lkcl | because if so that's incorrect | 14:21 |
lkcl | it should be a #define such as "DRAFT_SFFS_EXTENSION" or something like that | 14:23 |
lkcl | because those 32-bit instructions are *not* 64-bit SVP64-specific instructions | 14:23 |
lkcl | they *really* are *really* scalar 32-bit only scalar *really* scalar-only instructions. | 14:24 |
lkcl | which happen to be being proposed (as scalar instructions) absolutely nothing to do with SVP64 whatsoever in any way shape or form | 14:24 |
ghostmansd[m] | lkcl, SVP64 is just a shorthand which gets activated with -mlibresoc | 14:47 |
ghostmansd[m] | This just means "whenever that flag is active, enable this insn" | 14:48 |
ghostmansd[m] | But yeah, this is a misnomer. Any ideas for short name for the flag? | 14:48 |
ghostmansd[m] | Like we have PPCVLE, or POWER10, or like this | 14:49 |
lkcl | -mdraftsffs | 15:00 |
lkcl | SFFS is the "Scalar Fixed and Floating-Point Subset" | 15:01 |
lkcl | which is what these scalar instructions are all being added to | 15:01 |
lkcl | if you wanted to get fancy it could be called "-mdraft_ls012_sffs" and the commits refer to this https://ftp.libre-soc.org/opf_ext_rfc/ls012.pdf | 15:02 |
lkcl | ok those were quite easy to find https://bugs.libre-soc.org/show_bug.cgi?id=1068#c2 | 15:04 |
lkcl | you'd actually done a hell of a lot already | 15:07 |
lkcl | which is awesome | 15:14 |
markos | lkcl, what is the git for the website? I want to convert the chacha20 doc to mdwn format and make it accessible to the web, probably under the svp64 cookbook umbrella | 15:18 |
markos | nevermind... :) | 15:19 |
markos | just found it, under the bug report :) | 15:20 |
markos | lkcl, permission denied on libreriscv.git | 15:32 |
ghostmansd[m] | lkcl, thanks for sorting these out! | 15:46 |
ghostmansd[m] | I'll finish with removing pr everywhere, and switch to binutils flags | 15:46 |
markos | lkcl, FATAL: W any libreriscv markos DENIED by fallthru when I try to push | 16:50 |
markos | under cookbook/ | 16:51 |
markos | I'm just trying to add chacha20.mdwn there, I'm not (yet) adding another algorithm for the ticket | 16:52 |
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ghostmansd | lkcl, FYI: https://salsa.debian.org/Kazan-team/mirrors/openpower-isa/-/jobs/4165410 | 17:40 |
ghostmansd | Already fixed this in master | 17:40 |
ghostmansd | Perhaps we could've generated these from fields.text, but I'm not sure whether Form enum is not order-dependent | 17:40 |
lkcl | markos, 1 sec | 17:51 |
lkcl | done, try again | 17:52 |
lkcl | ghostmansd, ah yep it needs adding to the... ok you sorted it | 17:53 |
lkcl | toshywoshy, one to watch out for | 17:53 |
lkcl | https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=74a1b2ad43661599e3c3810f742149c17e83f542 | 17:53 |
ghostmansd | if this enum does not depend on order, we could simply grab anything we find in fields.text | 17:53 |
lkcl | i'd added these: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=f817539cbfb4fa73153369ce0f2ed9d1c23fca46 | 17:53 |
ghostmansd | Yep, I added CW and CW2 | 17:54 |
lkcl | ghostmansd, mmm.... i kiiinda prefer them to be explicit? it gives the opportunity to add comments (you can see MM=minmax) | 17:54 |
ghostmansd | yeah fair enough | 17:54 |
ghostmansd | I also like the explicitness of the enum | 17:55 |
lkcl | and also it's funny but if someone randomly adds something to fields.txt it's kinda good to have the error occur | 17:55 |
markos | lkcl, thanks | 17:55 |
lkcl | as a sort-of-not-exactly-deliberate double-check | 17:55 |
lkcl | yeah. | 17:55 |
markos | now to fix formatting :) | 17:55 |
lkcl | markos, looking forward to reading it, i have just added stubs for maxloc, pospopcnt and conflictd | 17:55 |
ghostmansd | we should perhaps at least have a better warning, not like "what the heck we lost some key", but rather "hey bruh you lost it in this tiny enum" | 17:56 |
ghostmansd | the default Python warning takes a while to understand what's going on | 17:56 |
markos | lkcl, well it's the same as the txt version so far, need to add the intro to VF mode that you asked, fix formatting and call it 'done' :) | 17:56 |
lkcl | niiice | 17:57 |
lkcl | ghostmansd, yes good call | 17:57 |
lkcl | markos, and probably "what the heck is indexing" :) | 17:57 |
markos | that too | 17:58 |
markos | hope to be done today | 17:58 |
markos | plan to work on SVP64 stuff by the end of this week, was too busy with arm stuff lately but that's done now -well the tickets that were overdue at least- so I have some extra time | 17:59 |
ghostmansd | ehem | 18:02 |
ghostmansd | have we lost stride? | 18:02 |
ghostmansd | ld/st | 18:02 |
ghostmansd | f*ck I sure missed a lot :-) | 18:02 |
ghostmansd | or at least I've completely forgotten that we lost it | 18:03 |
ghostmansd | rebasing binutils after regenerating the code, and hitting "WTF is stride" issue | 18:03 |
lkcl | elstride is still there, just a little different. | 18:04 |
ghostmansd | what I really like is that, whenever Python code is changed and I have a bravery to generate binutils code, I always end up with "something went wrong" instead of "hey, don't worry, we're separate projects" | 18:04 |
lkcl | whoopeee! | 18:05 |
lkcl | :) | 18:05 |
lkcl | https://libre-soc.org/openpower/sv/ldst/ | 18:05 |
lkcl | bit 4 (MSB0-numbering) of Mode in LDST_Imm | 18:05 |
ghostmansd | yeah exactly the page I;m looking into :-) | 18:05 |
ghostmansd | we used to have separate "stride" mode IIRC | 18:06 |
ghostmansd | with SEA, dz and sz | 18:06 |
lkcl | having got rid of predicate-result it was possible to bring back some priority to other mode-bits | 18:06 |
lkcl | that were previously sacrificed/limited | 18:07 |
lkcl | but still there are far too few Mode bits | 18:07 |
ghostmansd | aaargh we're lacking PI mode :-( | 18:07 |
ghostmansd | I'm resorting to simple/sat/ff for now | 18:08 |
lkcl | ack | 18:08 |
lkcl | btw note that PI - post-increment - is a temporary hack that i am hoping will not become permanent. | 18:08 |
lkcl | but it requires an astounding *forty five* new LD/ST instructions (including the shifted-and-update-post-increment ones) | 18:09 |
lkcl | if that bit is to be removed | 18:09 |
ghostmansd | you wrote it exactly when I wanted to ask whether I should raise a task to support it :-) | 18:09 |
lkcl | btw i deliberately didn't put the LD/ST-post-increment or the LD/ST-shifted instructions on the binutils TODO list | 18:10 |
lkcl | because it is an "either/or" situation for "/pi" in SVP64, or those (45) instructions in the *scalar* SFFS subset | 18:11 |
lkcl | LD/ST-with-shift is "EA = (RA) + (RB)<<sm" | 18:11 |
lkcl | no immediate variants involved there (absolutely no point whatsoever, to have an immediate shifted by another immediate) | 18:12 |
ghostmansd | ah, OK, I'll skip this one | 18:12 |
ghostmansd | either/or seems kinda hacky already per se | 18:12 |
ghostmansd | because the rest applies everywhere | 18:12 |
lkcl | it's why i didn't put them in the list, not least because there's no room available | 18:12 |
ghostmansd | or, well, almost | 18:12 |
lkcl | until PO9 is approved by the OPF ISA WG as a (new) 64-bit prefix space | 18:13 |
lkcl | https://libre-soc.org/openpower/sv/po9_encoding/ | 18:13 |
ghostmansd | damn :-) | 18:14 |
ghostmansd | anything else I missed? | 18:14 |
ghostmansd | seems like you guys changed a lot! | 18:14 |
ghostmansd | well I kinda vaguely recall EXT009 | 18:14 |
lkcl | there's a critical hard deadline coming up for Simple-V to get into Power ISA RFCs | 18:15 |
ghostmansd | > including VSX in future | 18:15 |
lkcl | hence i have had to scramble for the past 2 months, there's *15* RFCs now. | 18:15 |
lkcl | yes. | 18:15 |
ghostmansd | This frighthens a bit | 18:15 |
ghostmansd | holy cow | 18:15 |
ghostmansd | 15 RFCs? | 18:15 |
ghostmansd | did you even get a sleep while I was absent? | 18:15 |
lkcl | it's a massive task, classifying a whopping 750 instructions, so i am going *nowhere near that* | 18:16 |
lkcl | yep. | 18:16 |
lkcl | 5 for Simple-V (ls001 - po9; ls005 - XLEN; ls008-010 for management, format, and REMAP) | 18:16 |
lkcl | then there's 150 new instructions to propose, where ls012 does an "overview" of them all | 18:17 |
lkcl | if you read any of them and have questions or comments put them on the appropriate bugreport https://bugs.libre-soc.org/show_bug.cgi?id=1012 | 18:17 |
lkcl | and i have an excuse to throw at least EUR 500 your way | 18:18 |
ghostmansd | OK, but no sooner than I finish binutils | 18:18 |
ghostmansd | unlike Caius Iulius Caesar, I'm unable to handle several deeds at once :-) | 18:19 |
lkcl | no problem. if you're going to read them then as long as you demonstrate that (by putting something in the bugtracker) i can put in a budget | 18:19 |
lkcl | :) | 18:19 |
lkcl | frickin tell me about it | 18:19 |
lkcl | knowledge of how DCT REMAP works has almost completely gone. sigh | 18:19 |
ghostmansd | donnerwetter | 18:37 |
ghostmansd | that was so long and tiring rebase of binutils | 18:37 |
ghostmansd | lots of conflicts, the most disgusting was the one where I synced specifiers | 18:38 |
ghostmansd | syncing specifiers and later getting rid one of them... sigh | 18:38 |
ghostmansd | the code is so literally f*cked that I even moved it to a separate branch, svp64-nopr | 18:39 |
ghostmansd | now studying diff between what I had (svp64) and this one | 18:39 |
ghostmansd | we really, I stress, _really_ must eventually compare binutils asm/disasm with Python | 18:40 |
ghostmansd | I think the whole thing is doomed now | 18:40 |
ghostmansd | I will eventually get to this so that markos can use binutils :-) | 18:41 |
ghostmansd | markos, I promise, I won't let you down :-) | 18:41 |
ghostmansd | but it will take some time | 18:41 |
ghostmansd | I even tried squashing the changes into the original commits, like "support normal mode disassembly" | 18:43 |
ghostmansd | what I like about git is that it makes stuff appear as if it never existed, just if you use force push | 18:43 |
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programmerjake | <lkcl> "> "Our processor is not far..." <- i said that in 2020, which iirc was accurate then | 19:40 |
programmerjake | <lkcl> "> We will probably start working..." <- again, i said that in 2020, obviously that didn't happen | 19:42 |
programmerjake | lkcl: if/when we have some spare mode bits in SVP64, imho we should add parallel prefix sum, like parallel-reduce but produces a whole vector instead of some junk and a scalar | 20:04 |
programmerjake | and with /mrr should produce postfix-sum | 20:06 |
programmerjake | prefix sum has a whole list of applications: counting sort, radix sort, decoding gray code, and others | 20:13 |
programmerjake | nm about /mrr, it won't work like that | 20:22 |
programmerjake | created https://bugs.libre-soc.org/show_bug.cgi?id=1071 for parallel prefix sum | 20:31 |
lkcl | what's the difference to https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_preduce_yield.py;hb=HEAD ? | 21:22 |
programmerjake | replied here: https://bugs.libre-soc.org/show_bug.cgi?id=1071#c3 | 21:26 |
lkcl | ahh i remember those diagrams. | 21:40 |
lkcl | arrrgh i have yet more spec writing to do... | 21:44 |
lkcl | can you add prefix sum to remap_preduce_yield.py in as sparse/simple/short a fashion as possible? | 21:45 |
programmerjake | i can help... | 21:45 |
lkcl | it should be dead simple, add an optional loop-set at the end of the iterate function | 21:46 |
programmerjake | yeah, though that'll be later today, probably after you're asleep | 21:46 |
lkcl | i explained the options where it'll fit into the available SVSHAPE SPR (submode bits - aka SVSHAPE.skip) | 21:46 |
lkcl | no problem | 21:46 |
lkcl | i can do the twiddly-bits of shoe-horning it in to the infrastructure | 21:46 |
programmerjake | :) | 21:47 |
lkcl | if you can then do the unit tests in test_caller_svp64_preduce.py in a couple of days? | 21:47 |
lkcl | it's.... dog-awful... | 21:47 |
programmerjake | yeah | 21:47 |
lkcl | bits named this but are being used for that | 21:47 |
programmerjake | can you add a todo list in the top comment so i don't forget? | 21:48 |
lkcl | it does the job but could really do with the same sort of "XYZ-Form" treatment as the opcodes | 21:48 |
lkcl | sure | 21:48 |
lkcl | and who does what | 21:48 |
lkcl | gimme a mo | 21:48 |
lkcl | eek 10mins till ISA WG meeting | 21:48 |
lkcl | later | 21:48 |
programmerjake | ttyl | 21:48 |
lkcl | budget assigned, EUR 2000 | 21:48 |
programmerjake | 😁 | 21:50 |
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toshywoshy | lkcl: don't you mean 1h 10m ? | 22:04 |
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