Wednesday, 2023-05-31

lkclindeed00:08
* lkcl thinks00:08
lkclit doesn't matter "per se" because RA=0 is an illegal instruction00:20
lkclghostmansd, hang on, reading the spec it looks like RA_OR_ZERO for ldu is a bug00:23
lkclit should just be "RA"00:25
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programmerjakeoh, it just occurred to me, since memory accesses aren't overridden by elwid, we'll need 16-bit fp loads/stores10:18
programmerjakelkcl: what do you think?10:18
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ghostmansd[m]lkcl, please also check this: https://libre-soc.org/irclog/%23libre-soc.2023-05-30.log.html#t2023-05-30T18:32:2812:15
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lkclprogrammerjake, arrrgh good point16:06
lkclghostmansd, it is a bug.16:06
lkclreading the spec you cannot have RA=0 for ldu or ldux16:08
lkclthose instructions *both* need to have their csv lines changed to ...,RA,....,RA,...16:08
lkclghostmansd, i'm doing EXTRA332 at the moment16:09
lkclprogrammerjake, ok actually now i think about it that's not such a bad idea16:34
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ghostmansdlkcl, you reply demonstrates that you didn't read the question.18:20
ghostmansdI understand you have a lot to do besides that.18:20
ghostmansdSo I discovered the reply on my own.18:20
ghostmansdPlease read the thread before replying, otherwise it just wastes your time.18:22
ghostmansdAnd wastes mine too.18:22
ghostmansdThe reply is: yes there can be different extras for the same operand. Example is rlwimi instruction, probably others.18:23
ghostmansd20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,rlwimi,M,18:23
ghostmansdOr, well, the correct is "not different extras", but rather same extra appearing twice on different indexes.18:24
ghostmansdrlwimi,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,018:25
ghostmansdd:RA leads to extra0, s:RA leads to extra1.18:26
ghostmansdThat was the original question.18:26
ghostmansdAnd, by the way, this leads to failure: $(echo "sv.rlwimi 3, 1, 5, 20, 6" | SILENCELOG=true pysvp64asm)18:30
ghostmansdTriggering the exact assertion error which checks for different extras.18:30
ghostmansdI'm adding a test for this instruction into disassembly tests.18:31
ghostmansdList of broken instructions is here: https://bugs.libre-soc.org/show_bug.cgi?id=1093#c218:42
ghostmansdRaised a separate task: https://bugs.libre-soc.org/show_bug.cgi?id=109818:44
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octaviusI'll be about 10min late for the meeting today20:46
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programmerjakesubmitted https://bugs.libre-soc.org/show_bug.cgi?id=1099 for 16-bit fp load/stores, didn't have time to add see-also/blocks yet21:03
programmerjakei'll be a few min late21:04
lkclghostmansd, so sorry massive headache21:16
lkclghostmansd,  brilliant will talke a look21:17
ghostmansdthat's OK, np21:17
ghostmansddo we have a meeting today?21:17
ghostmansdI've been thinking of finally participating :-)21:17
lkclgood idea to put in test_pysvp64dis.py21:18
ghostmansdI'm refactoring extras to simplify the visitor idea and fix RA0/RT0 issues21:18
ghostmansdso please don't touch these places now21:19
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programmerjakelkcl, thx for adding see-alsos!22:40
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lkclalways needed otherwise the bugs get lost as noise22:46
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