| programmerjake | lkcl: i'm running into an issue where I'm adding spr support to ExpectedState but I'm getting a mismatch for fp traps for HSRR1 which should be zero according to the spec. but isn't -- in caller.py:267 it hack aliases HSRR* to SRR*, can I comment out that hack or do you still need it? | 07:13 |
|---|---|---|
| programmerjake | I expect no openpower-isa tests need it (am currently re-running tests after noticing I forgot to comment out the setters and not just the getters) | 07:14 |
| programmerjake | yup, nothing needs it in openpower-isa according to pytest | 07:17 |
| programmerjake | oh, wait, I'll just use a hacky workaround for your hacky workaround...I'll clear SRR* while trying to read HSRR* in SimState, that way it gets the correct values whenever you remove the caller.py hack, but still gets zeros for HSRR* meanwhile so matches the expected state | 07:20 |
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| octavius | I tried running 'make tests' in media dir, https://libre-soc.org/docs/pypowersim/ | 17:56 |
| octavius | Currently make fails with: | 17:56 |
| octavius | cp audio/mp3/mp3_0_apply_window_float.s audio/mp3/mp3_0_apply_window_float.s.sv | 17:56 |
| octavius | powerpc64le-linux-gnu-as -mlibresoc -c audio/mp3/mp3_0_apply_window_float.s.sv -le -o audio/mp3/mp3_0_apply_window_float.s.o | 17:56 |
| octavius | Assembler messages: | 17:56 |
| octavius | Error: invalid switch -mlibresoc | 17:56 |
| octavius | Error: unrecognized option -mlibresoc | 17:56 |
| octavius | make: *** [Makefile:36: audio/mp3/mp3_0_apply_window_float.bin] Error 1 | 17:56 |
| octavius | Running latest git commit: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=066134b401fca5dac03a292703e805a9f87d59fa | 17:56 |
| octavius | But it looks like the -mlibresoc flag was added by: | 17:56 |
| octavius | https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=0e65b3c53bd5456a74878aeb48898665317ccb6a | 17:56 |
| octavius | Are there some extra dependencies that provide a definition for -mlibresoc? | 17:59 |
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| ghostmansd | lkcl, yet another question on extras | 18:14 |
| ghostmansd | the code currently implemented in GPROperand (and by other reg-like-operand-types) "yields" them | 18:15 |
| ghostmansd | this actually is in ExtendableOperand here: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l1242 | 18:16 |
| ghostmansd | And this code acts as if we might have several extras per operand... | 18:17 |
| ghostmansd | however, we skip identical bits | 18:17 |
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| ghostmansd | so we only need to check whether say in_sel extra is different than say out_extra | 18:18 |
| ghostmansd | But we still treat "bits" variable as tuple: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l1267 | 18:19 |
| ghostmansd | My question now is... | 18:19 |
| ghostmansd | Do we really have multiple values in this tuple, or it's just that this algorithm I wrote is completely stupid? | 18:20 |
| ghostmansd | Because I cannot understand how _one_ operand can have _multiple_ extras | 18:20 |
| ghostmansd | and this also looks wrong now: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l1190 | 18:21 |
| ghostmansd | I think some parts of the original code which I looked into resulted into this | 18:21 |
| ghostmansd | but it seems that any self.idx should return just only 1 value -- SVExtra enum value | 18:21 |
| ghostmansd | Please confirm that these statements above are correct, this code is horrendous, as the whole extra mapping process. | 18:22 |
| ghostmansd | lkcl, ignore everything above for a while, let's take a concrete example | 18:32 |
| ghostmansd | ldu,LDST_IMM,,2P,EXTRA3,EN,d:RT,d:RA;s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,RA | 18:32 |
| ghostmansd | This will yield (extra1, extra1) | 18:32 |
| ghostmansd | My point is that we should not bother about this stuff highlighting that there are two extra mappings, s:RA and d:RA, because they should map to exactly the same extra (extra1) | 18:33 |
| ghostmansd | And we only need to check whether there's a conflict and output extra1 value instead of (extra1, extra1) tuple | 18:34 |
| ghostmansd | lkcl, remember the yesterday's question about can we have both RA and RA_OR_ZERO? | 19:10 |
| ghostmansd | ldu,LDST_IMM,,2P,EXTRA3,EN,d:RT,d:RA;s:RA,0,0,RA_OR_ZERO,0,0,RT,0,0,RA | 19:11 |
| ghostmansd | here it goes: out2 is RA, in1 -- RA_OR_ZERO | 19:11 |
| ghostmansd | from my perspective such things should either be both RA_OR_ZERO | 19:11 |
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| programmerjake | i'll be a few min late for the meeting | 20:01 |
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| ghostmansd | I've updated the code logic to sync XX with XX_OR_ZERO | 21:12 |
| ghostmansd | https://libre-soc.org/irclog/%23libre-soc.2023-05-30.log.html#t2023-05-30T18:32:28 | 21:13 |
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| programmerjake | note from meeting, i'd still like to remove the hack alias hsrr0/1 to srr0/1 | 22:41 |
| programmerjake | lkcl: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/caller.py;h=9dd55b869e9d9536dc6cdf27327627a4ba8ed55f;hb=HEAD#l267 | 22:43 |
| programmerjake | as mentioned yesterday | 22:43 |
| lkcl | programmerjake, yes please don't remove HSRR mappings, they are critically important for Microwatt interoperability. | 22:46 |
| lkcl | programmerjake, sorry they have to stay | 22:46 |
| lkcl | ghostmansd, programmerjake, sorry i've been dealing literally the entire day with answering SVP64-related email issues i'm only just catching up | 22:48 |
| lkcl | > <ghostmansd> from my perspective such things should either be both RA_OR_ZERO | 22:49 |
| programmerjake | np, i understand | 22:49 |
| lkcl | yyyyeesss i think you're right, in principle, except there is no concept of "RA=0-as-an-output", it's actually an illegal instruction. i think | 22:50 |
| lkcl | https://ftp.libre-soc.org/PowerISA_10_public_v3.1.pdf | 22:50 |
| lkcl | p51 | 22:50 |
| lkcl | Load Doubleword with Update Indexed | 22:51 |
| lkcl | X-form | 22:51 |
| lkcl | ldux RT,RA,RB | 22:51 |
| lkcl | If RA=0 or RA=RT, the instruction form is invalid. | 22:51 |
| lkcl | what we have to watch out for - ha ha - is that that is now | 22:51 |
| lkcl | if EXTRA_EXTENDED(RA)=0 or EXTRA_EXTENDED(RA)=EXTRA_EXTENDED(RT), the instruction form is invalid | 22:52 |
| programmerjake | i think his complaint was that RA as src and RA as dest had different forms RA/RA_OR_ZERO | 22:56 |
| programmerjake | and he wants that fixed | 22:57 |
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