Tuesday, 2023-05-30

programmerjakelkcl: i'm running into an issue where I'm adding spr support to ExpectedState but I'm getting a mismatch for fp traps for HSRR1 which should be zero according to the spec. but isn't -- in caller.py:267 it hack aliases HSRR* to SRR*, can I comment out that hack or do you still need it?07:13
programmerjakeI expect no openpower-isa tests need it (am currently re-running tests after noticing I forgot to comment out the setters and not just the getters)07:14
programmerjakeyup, nothing needs it in openpower-isa according to pytest07:17
programmerjakeoh, wait, I'll just use a hacky workaround for your hacky workaround...I'll clear SRR* while trying to read HSRR* in SimState, that way it gets the correct values whenever you remove the caller.py hack, but still gets zeros for HSRR* meanwhile so matches the expected state07:20
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octaviusI tried running 'make tests' in media dir, https://libre-soc.org/docs/pypowersim/17:56
octaviusCurrently make fails with:17:56
octaviuscp audio/mp3/mp3_0_apply_window_float.s audio/mp3/mp3_0_apply_window_float.s.sv17:56
octaviuspowerpc64le-linux-gnu-as -mlibresoc -c audio/mp3/mp3_0_apply_window_float.s.sv -le -o audio/mp3/mp3_0_apply_window_float.s.o17:56
octaviusAssembler messages:17:56
octaviusError: invalid switch -mlibresoc17:56
octaviusError: unrecognized option -mlibresoc17:56
octaviusmake: *** [Makefile:36: audio/mp3/mp3_0_apply_window_float.bin] Error 117:56
octaviusRunning latest git commit: https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=066134b401fca5dac03a292703e805a9f87d59fa17:56
octaviusBut it looks like the -mlibresoc flag was added by:17:56
octaviusAre there some extra dependencies that provide a definition for -mlibresoc?17:59
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ghostmansdlkcl, yet another question on extras18:14
ghostmansdthe code currently implemented in GPROperand (and by other reg-like-operand-types) "yields" them18:15
ghostmansdthis actually is in ExtendableOperand here: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l124218:16
ghostmansdAnd this code acts as if we might have several extras per operand...18:17
ghostmansdhowever, we skip identical bits18:17
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ghostmansdso we only need to check whether say in_sel extra is different than say out_extra18:18
ghostmansdBut we still treat "bits" variable as tuple: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l126718:19
ghostmansdMy question now is...18:19
ghostmansdDo we really have multiple values in this tuple, or it's just that this algorithm I wrote is completely stupid?18:20
ghostmansdBecause I cannot understand how _one_ operand can have _multiple_ extras18:20
ghostmansdand this also looks wrong now: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_insn.py;h=41a0c88e88f7dbeb21ef8df15b2e2205e20b196f;hb=refs/heads/master#l119018:21
ghostmansdI think some parts of the original code which I looked into resulted into this18:21
ghostmansdbut it seems that any self.idx should return just only 1 value -- SVExtra enum value18:21
ghostmansdPlease confirm that these statements above are correct, this code is horrendous, as the whole extra mapping process.18:22
ghostmansdlkcl, ignore everything above for a while, let's take a concrete example18:32
ghostmansdThis will yield (extra1, extra1)18:32
ghostmansdMy point is that we should not bother about this stuff highlighting that there are two extra mappings, s:RA and d:RA, because they should map to exactly the same extra (extra1)18:33
ghostmansdAnd we only need to check whether there's a conflict and output extra1 value instead of (extra1, extra1) tuple18:34
ghostmansdlkcl, remember the yesterday's question about can we have both RA and RA_OR_ZERO?19:10
ghostmansdhere it goes: out2 is RA, in1 -- RA_OR_ZERO19:11
ghostmansdfrom my perspective such things should either be both RA_OR_ZERO19:11
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programmerjakei'll be a few min late for the meeting20:01
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ghostmansdI've updated the code logic to sync XX with XX_OR_ZERO21:12
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programmerjakenote from meeting, i'd still like to remove the hack alias hsrr0/1 to srr0/122:41
programmerjakelkcl: https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/caller.py;h=9dd55b869e9d9536dc6cdf27327627a4ba8ed55f;hb=HEAD#l26722:43
programmerjakeas mentioned yesterday22:43
lkclprogrammerjake, yes please don't remove HSRR mappings, they are critically important for Microwatt interoperability.22:46
lkclprogrammerjake, sorry they have to stay22:46
lkclghostmansd, programmerjake, sorry i've been dealing literally the entire day with answering SVP64-related email issues i'm only just catching up22:48
lkcl> <ghostmansd> from my perspective such things should either be both RA_OR_ZERO22:49
programmerjakenp, i understand22:49
lkclyyyyeesss i think you're right, in principle, except there is no concept of "RA=0-as-an-output", it's actually an illegal instruction.  i think22:50
lkclLoad Doubleword with Update Indexed22:51
lkcl                               X-form22:51
lkclldux    RT,RA,RB22:51
lkclIf RA=0 or RA=RT, the instruction form is invalid.22:51
lkclwhat we have to watch out for - ha ha - is that that is now22:51
lkclif EXTRA_EXTENDED(RA)=0 or EXTRA_EXTENDED(RA)=EXTRA_EXTENDED(RT), the instruction form is invalid22:52
programmerjakei think his complaint was that RA as src and RA as dest had different forms RA/RA_OR_ZERO22:56
programmerjakeand he wants that fixed22:57
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