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lkcl | programmerjake, indeed it does. there should be no editing of the auto-generated json files, under any circumstances. it would mean that what NLnet receive and have in their RFP system is **DIFFERENT** from what is in the bugtracker. | 10:22 |
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lkcl | that means that when the EU Auditor comes to look at the two, they will think we are attempting to defraud them by claiming money for one task but actually doing another | 10:22 |
lkcl | (in the extreme case) | 10:22 |
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octavius | thanks for reminding me to use the microwatt repo for verilator lkcl, the hello world code runs on the modified core! Now just need some svp64 machine code | 14:20 |
octavius | So I'll look at pypowersim | 14:20 |
octavius | see bug 1127 | 14:20 |
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octavius | thanks lkcl | 14:45 |
markos_ | octavius, let me know if you need any help with pypowersim and svp64 code | 14:45 |
markos_ | this is great news | 14:45 |
octavius | sure | 14:45 |
markos_ | if you manage to run even a single svp64 instruction it's a huge milestone | 14:45 |
octavius | Taking a break now. Since I'm going to see James tomorrow, I will make sure something is running by the end of today | 14:46 |
markos_ | is it possible you check the contents of registers on the fpga at a given moment? | 14:48 |
octavius | There is a debug interface (DMI), which is the same as Microwatt one | 14:50 |
octavius | should be available both on verilator and fpga. Although I don't know how to use it | 14:51 |
markos_ | well, if you can do that, you could take the asm code of a simple unit test even and run it | 14:55 |
markos_ | and then check the contents of the registers | 14:55 |
markos_ | but I admit I don't know how that is done on fpgas | 14:55 |
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octavius | markos_, can you check if these two assembly instructions are correct? | 19:49 |
octavius | I want to do a brain-dead simple example in svp64 (because my brain is melting): | 19:49 |
octavius | Horizontal-First, VL=3, add immediate 3 to registers 17, 18, 19. | 19:49 |
octavius | setvl 0, 0, 3, 0, 1, 0 # RT,RA both r0, VL=3, vf=0, vs=1, ms=0 | 19:49 |
octavius | sv.addi 17.v, 17.v, 3 | 19:49 |
programmerjake | you need ms=1 and the syntax for vector-mode registers is *17, 17.v is the old deprecated syntax | 19:52 |
octavius | Ah thanks, I saw the old syntax on the overview page, V-F section | 19:52 |
programmerjake | so: | 19:53 |
programmerjake | setvl 0, 0, 3, 0, 1, 1 | 19:53 |
programmerjake | sv.addi *17, *17, 3 | 19:53 |
octavius | thanks | 19:53 |
programmerjake | ms=1 sets MAXVL too, you can think of it as an upper bound on how big VL can be, so if you don't set it, then it could limit VL to something smaller than you want, depending on what MAXVL was set to previously | 19:59 |
octavius | Ah of course, because it gets the value from SVSTATE, which may have been set to something else | 20:00 |
programmerjake | yup! | 20:02 |
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