lkcl | https://bugs.libre-soc.org/show_bug.cgi?id=389#c1 | 14:37 |
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lkcl | about the conversion to SVG this one's a good place to start https://libre-soc.org/3d_gpu/comp_unit_req_rel.jpg | 14:37 |
lkcl | and you can see we found some SVG logic gates that are CC licensed | 14:37 |
lkcl | mePy2[m]: one idea here is that with SVG it is possible to use a javascript web real-time circuit simulator to actually show the gates | 14:38 |
lkcl | and have the SVG diagram "light up" | 14:38 |
lkcl | so one important thing is to include names on objects and sub-objects | 14:39 |
lkcl | rather than have the editor create names "$1" "$2" "$3" etc. | 14:39 |
lkcl | that way the javascript can be written to tree-walk the DOM of the SVG when it's imported and find the right "thing" to highlight | 14:40 |
lkcl | ah - jacob found this https://bugs.libre-soc.org/show_bug.cgi?id=389#c4 | 14:40 |
mePy2[m] | Well. My “plan”. Or better, what I could do, is to make all the images. And then someone should look at them for review. But I think I would not use the exact same e.g. AND logic port image for all my drawings. Instead I think I would find much quicker to just draw each ports for each image. Am I clear enough? | 20:55 |
mePy2[m] | Anyway, what about using a software for creating circuits directly instead? | 21:00 |
mePy2[m] | F.e. this (I use it at school) http://www.falstad.com/circuit/ | 21:00 |
mePy2[m] | lkcl: | 21:01 |
mePy2[m] | * Well. My “plan”. Or better, what I could do, is to make all the images. And then someone should look at them for review. But I think I would not use the exact same e.g. AND logic port image for all my drawings. Instead I think I would find much quicker to just draw each "set of ports" for each image. Am I clear enough? | 21:29 |
lkcl | ahhh yeah circuitjs. we looked at that and found that because it uses Google Web Toolkit it consumes 100% CPU. wark-wark :) | 21:37 |
lkcl | if you think you can do that one ( https://libre-soc.org/3d_gpu/comp_unit_req_rel.jpg ) quicker without using the CC-licensed SVG logic gates, great, go for it | 21:39 |
lkcl | but, start with just that one diagram https://libre-soc.org/3d_gpu/comp_unit_req_rel.jpg | 21:39 |
mePy2[m] | About that GWT thing, yeah. It was nice though. | 22:27 |
mePy2[m] | Anyway, for a quick work I will use a commercial program I already have on my Mac. But if it is a problem I think it should not be a real issue to get used to Inkscape. | 22:27 |
mePy2[m] | Ok... well, it was not as fast as I expected it to be. | 23:49 |
mePy2[m] | Anyway I made the SVG image. I am missing only the text next to the gates. One is "op en", the other one is?... lkcl | 23:49 |
lkcl | mePy2[m]: hmm i have to look at the original PDF | 23:52 |
lkcl | it is "cl something" meaning "close something" | 23:52 |
lkcl | oh wait! open | 23:53 |
lkcl | and close | 23:53 |
lkcl | lol | 23:53 |
mePy2[m] | close what? | 23:53 |
mePy2[m] | :D | 23:53 |
mePy2[m] | I thought more "op en" --> "opcode enable" | 23:54 |
mePy2[m] | Dunno thought. | 23:55 |
mePy2[m] | * Dunno though | 23:55 |
mePy2[m] | Anyway, what should I do now? Where I could put it? | 23:55 |
mePy2[m] | It is quite late here, bed time now :) | 23:56 |
mePy2[m] | oh sh**t... "open" and "close" lol! | 23:57 |
mePy2[m] | ... | 23:58 |
mePy2[m] | Ok, waiting for instructions now :) | 23:58 |
mePy2[m] | Good night :) | 23:58 |
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