Saturday, 2021-03-13

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* lkcl_ is now just wondering if SVSTATE should not be considered to be like MSR09:40
lkcl_mtsvstate, mfsvstate, just like mtmsr and mfmsr10:21
lkcl_ahh i think i know why IBM has sc in an entire major opcode even though there's nothing in it11:37
lkcl_it may be because it's "simple" to decode and consequently can be in the instruction fetch phase11:38
lkcl_doesn't need to be part of the instruction decoder11:38
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* lkcl_ added the pseudocode for subvl12:07
lkcl_nobody do a git submodule update, i haven't checked it!12:08
lkcl_syntax errors pass...12:19
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lkcl_programmerjake, arg you were right, adding RT_OR_ZERO will be a royal nuisance16:06
lkcl_the pseudocode parser can't cope, and it's sufficiently complex i can't be arsed to edit it :)16:07
lkcl_but more than that, Rc=1 mode would otherwise be completely different16:07
lkcl_if however RT is always written to then Rc=1 mode is no different16:07
lkcl_pain in the neck but hey16:07
lxo seems like a project we could collaborate with.  it would be nice to have libre-soc among the hardware designs they're working with16:33
lkcl_lxo: nice find!16:47
lkcl_the single-core gigabit ethernet router IC would qualify because we'll be using entirely libre-licensed RTL.16:48
lkcl_opencores SDRAM16:48
lkcl_which is only 133 mhz SDR1 but is entirely libre16:49
lxolkcl_, can't take credit for it.  ricardo morte ferrer pointed me at it.  he's in touch with Kai Mertens (who's involved/leading? the project), and I suppose Ricardo could get us all in touch16:51
lkcl_i'll email him, cc you16:53
lxooh, so no introductions needed.  cool16:53
lkcl_sent, let's see how it goes16:57
lkcl_yeah the gigabit router ASIC needs no proprietary HDL at all, including the PLL16:58
lkcl_which i think the Freedom U310 did actually have to have closed-source PLL and Analog ADC/DAC cells16:58
lkcl_and that's listed on their site16:58
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awyglelkcl_: is it safe to assume that any PartitionedSignals which are participating in an operation must have the same partition bits set?23:38
awyglemeaning you won't have "a + b" where a is a1/a2/a3/a4 and b is b1b2b3/b4?23:39
lkcl_awygle, yes absolutely23:41
awygleok. and for the m.If stuff, is it safe to assume that any PartitionedSignal referenced in the body will have the same partition bits set as the signal(s) in the condition?23:42
lkcl_ohh yes23:42
awygleok. and for the m.If stuff, is it safe to assume that every signal in the body will be a PartitionedSignal?23:42
lkcl_in fact, now that i think about it, there should really be some checking (if that's practical)23:42
lkcl_ahh... no, that's not safe23:43
lkcl_shift is a good example23:43
awyglein that case what behavior should occur if you have m.If(x == 5): a.eq(b) where some parts of x are 5 and other aren't (where a and b are not partitioned)?23:43
lkcl_the shift amount can be a Const, Signal, or another PartitionedSignal23:43
lkcl_err... let me think that through :)23:44
awygleah ok, i should have restricted my statement more - can we assume all LHS signals, all driven signals, in the bodies will be PartitionedSignals?23:44
lkcl_yes that's very reasonable23:45
lkcl_that's a perfectly reasonable assumption, to the point where it might make sense to make it a hard requirement23:45
awyglei agree, i'm not sure there's any way to make this make sense without that assumption23:46
lkcl_one thing: anything involving m.If() should basically assume that booleans are now arrays-of-booleans23:46
lkcl_in effect23:47
lkcl_rather than (say) a 2x32 being 0b00010001 in the underlying signal23:47
lkcl_it should be 0b1111111123:47
lkcl_where AAAA is boolean[1] and BBBB is boolean[0]23:48
lkcl_the reason is this:23:48
lkcl_it then becomes possible to use each bit in the PartitionedMux *without* any complications23:49
awyglei was thinking it might make sense to introduce a ParititonedBool or similar as the result of a PartitionedSignal comparison, to track such cases. it will be easier to deal with if the invariant is encoded in the type system rather than just a promise among developers23:49
lkcl_yes that idea popped into my head a couple months back23:49
lkcl_i didn't verbalise it / write it down / give it due attention23:50
lkcl_it's a good idea23:50
lkcl_ah i know why i didn't pursue it: it's because there's no equivalent in nmigen23:50
lkcl_there's no Bool in nmigen23:51
awyglethat's true23:51
lkcl_because Signal(1) performs double-duty23:51
* lkcl_ thinks23:51
lkcl_if Bool existed this would be a no-brainer decision23:52
lkcl_inventing PartitionedBool without it expands the scope somewhat23:53
lkcl_would you be happy to defer that one until later?23:53
awygleit may become a requirement for detecting the "PartitionedSignal If" case, but if it doesn't, then sure23:53
lkcl_ok yes makes sense23:54
awygle(that is, the easiest way to detect "is this a ParititionedSignal If" is "what is the type of the condition", but there may be other ways)23:54
lkcl_yeah there's some code i glossed over in m.If that involved assessing if the input is a boolean23:54
awyglebut it's not as easy as "if len(sig) > 1" because of bool coercions23:55
lkcl_it'd involve, "is this of type PartitionedSignal"23:56
lkcl_ah i know23:56
lkcl_a function as part of Value which tests if something is "bool-like"23:57

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