| lkcl | Chips4Makers: *great* to have a post-layout simulation | 13:10 |
|---|---|---|
| Chips4Makers | @lkcl: final target is that one should be able to do it with FreePDK45 version for people who don't have access to the .18 TSMC NDA PDK. | 14:00 |
| lkcl | frickin fantastic. love it. | 15:58 |
| lkcl | Chips4Makers: just sorting out the tags | 15:59 |
| * lkcl found this https://stackoverflow.com/questions/1028649/how-do-you-rename-a-git-tag | 15:59 | |
| lkcl | Chips4Makers: new tag name is 24jan2021_ls180 which i just checked does not cause scmsetuptools to barf | 16:02 |
| Chips4Makers | @lkcl: The litex stuff all comes from the enjoy-digital repos on github ? | 16:20 |
| Chips4Makers | @lkcl: still problems with installing libresoc's c4m-jtag: | 16:33 |
| Chips4Makers | ... | 16:33 |
| Chips4Makers | raise InvalidVersion("Invalid version: '{0}'".format(version)) | 16:33 |
| Chips4Makers | pkg_resources.extern.packaging.version.InvalidVersion: Invalid version: '24jan2021_ls180' | 16:33 |
| Chips4Makers | This is python version 3.9.2 (from conda), setuptools 52.0.0 | 16:33 |
| lkcl | Chips4Makers, yes | 16:50 |
| lkcl | ah fer f'''s sake | 16:50 |
| lkcl | ok gimme 1 sec to delete that. | 16:50 |
| lkcl | Chips4Makers: ah we've never tested with python 3.9. 3.7 and 3.8 only | 16:52 |
| lkcl | ii python3-setuptools 52.0.0-3 | 16:52 |
| lkcl | should be good. | 16:53 |
| lkcl | re-running "python3 setup.py develop" in c4m-jtag now | 16:53 |
| lkcl | succeeds. | 16:53 |
| lkcl | Installed /home/lkcl/src/libresoc/c4m-jtag | 16:53 |
| lkcl | Processing dependencies for c4m-jtag===24jan2021ls181.dev2-gf9e5962 | 16:53 |
| lkcl | let me just blow it away see what happens... | 16:54 |
| lkcl | yep works fine | 16:55 |
| Chips4Makers | Seems PEP440 is enfoced on my side: https://www.python.org/dev/peps/pep-0440/ | 16:56 |
| klys | is there further progress on the chip layout that will implement kazan? | 16:56 |
| lkcl | kazan is a vulkan software driver to be using hardware-acceleration opcodes | 16:57 |
| Chips4Makers | Anyway I removed tags locally and added v0.0.0 tags to get it installed. | 16:58 |
| lkcl | ok good call | 16:58 |
| klys | I heard it was frozen because there was a chip vendor working on it | 16:58 |
| lkcl | there is no progress on a chip layout doing kazan because we have not started that | 16:58 |
| klys | okay thank you | 16:59 |
| lkcl | oh you mean the founder of chipeleven betraying the trust we placed in them? | 16:59 |
| klys | I would know nothing about such things | 16:59 |
| lkcl | put us behind by at least a year. | 16:59 |
| lkcl | the plan is to do this 180nm test ASIC first | 17:00 |
| lkcl | then either a 180 or 130nm one to be taped-out next year that is fully pipelined | 17:00 |
| lkcl | when that's working *then* we will have the confidence to drop USD 6 to 8 million on a quad-core 1.5 to 2ghz 22nm SoC | 17:01 |
| lkcl | and that's the point at which kazan (and the MESA 3D driver) and all other software will run. | 17:01 |
| klys | thank you much. | 17:02 |
| lkcl | no problem. | 17:04 |
| lxo | would anyone object if I were to offer GCC mentoring/tutoring by enlisting volunteers to implement parts of the libre-soc ISA extensions? | 17:11 |
| lkcl | lxo: great! | 17:12 |
| lkcl | not at all, particularly given that they'd be able to receive some of the NLnet donation for doing so | 17:12 |
| lxo | I was thinking of offering such mentoring/tutoring as part of the efforts to reduce gender imbalance in the GCC community, and thought libre-soc might be a wonderful opportunity to make a win-win out of it | 17:13 |
| lkcl | yes, great idea | 17:13 |
| lxo | are there any constraints WRT gender-related positive discrimination? | 17:13 |
| lkcl | Bob Podolski's research clearly showed that teams work better when there's a 50-50 balance | 17:14 |
| lkcl | absolutely none whatsoever. | 17:14 |
| lxo | beautiful, thanks | 17:14 |
| danielp3344 | 'positive discrimination'? | 17:23 |
| lxo | I'm not sure that's the right term in English. I'd appreciate advice on what the correct term for that is. in pt_BR the term translates literally as 'affirmative action' | 17:24 |
| lxo | as in, action intended to reverse prejudicial discrimination and correct imbalances arising from it | 17:25 |
| lxo | oh, hey, danielp3344, glad to see you here! :-) | 17:26 |
| danielp3344 | IE attempting to artificially raise the number of individuals from an under represented group? | 17:26 |
| danielp3344 | lxo: you too :P | 17:27 |
| lxo | countering the artificial underrepresentation, yeah | 17:27 |
| lkcl | lxo: if you got people responding (any people), i'd prefer that you considered them on technical merit | 17:27 |
| lkcl | that said i have no problem with the "marketing message" going out that invites under-represented people | 17:28 |
| danielp3344 | I'm not sure I fit the criteria but I gave notice at my current job last week, so by the end of next week I'll have a few months of time to devote to a new project | 17:28 |
| lkcl | danielp3344: some cross-over, there, with what i just wrote :) | 17:28 |
| lxo | I'd like to make this personal effort to reduce gender imbalance, that is recognized as a problem in the GCC community | 17:28 |
| danielp3344 | I have to say I agree with lkcl, encouraging minorities is fine as long as you don't turn away legitimate talent | 17:28 |
| lkcl | danielp3344: everyone is welcome. | 17:28 |
| lkcl | got it in one, danielp3344 | 17:29 |
| lkcl | http://libre-soc.org/charter/discussion | 17:29 |
| lkcl | i added the dilbert cartoons last week :) | 17:29 |
| lxo | that doesn't mean I could not offer similar tutoring to danielp3344 or others, but I'd really like to focus on that goal | 17:29 |
| danielp3344 | If I might get philosophical for a second, does gender imbalance matter? | 17:30 |
| danielp3344 | As long as certain groups aren't actively being treated badly that is | 17:30 |
| lkcl | y'know... in china i was stunned to find that there isn't a problem with gender imbalance in science and maths, at all. | 17:30 |
| klys | did GCC mean "gnu compiler collection" or what? | 17:30 |
| lkcl | klys: yes. | 17:31 |
| lkcl | it includes ada, fortran, many others. kinda cool | 17:31 |
| lxo | it matters so much in the GCC community that they're presenting it as an excuse to expel RMS from the steering committee | 17:31 |
| lkcl | sigh | 17:31 |
| danielp3344 | lxo: but why does it matter? | 17:31 |
| lxo | I want to call the BS on that | 17:32 |
| lkcl | danielp3344: what's your background btw? | 17:32 |
| danielp3344 | lkcl: ermmm, complicated | 17:32 |
| danielp3344 | dropped out of college with a fraction of a math degree, currently working in manufacturing | 17:33 |
| lxo | real action as opposed to fake gestures with very obvious undisclosed intents | 17:33 |
| danielp3344 | my computing career has been entirely self taught | 17:33 |
| lkcl | when i went to IIT Madras University i learned that there's a Govt funding Programme to provide full indefinite maternity leave for women, and grants as well | 17:33 |
| * danielp3344 considers himself a very under represented group :P | 17:33 | |
| lkcl | result: *thirty percent* women in the Masters and PhD Programme in the RISE Group, doing RISC-V hardware | 17:34 |
| lkcl | danielp3344: nice. | 17:34 |
| lxo | then you'll probably qualify :-D | 17:34 |
| danielp3344 | :D | 17:34 |
| danielp3344 | I would say I have good experience with C and working knowledge of compilers and CPUs | 17:35 |
| danielp3344 | but would like to learn more and contribute to a cool project | 17:35 |
| lkcl | nice | 17:35 |
| lkcl | well, this is about as cool as it gets to be honest | 17:35 |
| danielp3344 | I've noticed lol | 17:35 |
| lxo | I suppose I could ask applicants to state not only what their background is and why they're interested, but also what underpresent strengths they'd bring to the community | 17:36 |
| danielp3344 | Unfortunately I'm currently on break at work but I will return this evening | 17:36 |
| lkcl | have you seen the "SIMD considered harmful" article? https://www.sigarch.org/simd-instructions-considered-harmful/ | 17:36 |
| lkcl | ok | 17:36 |
| lkcl | danielp3344: if you're around 22:00 UTC we've a jitsi meeting tomorrow | 17:37 |
| lkcl | klys, ^ | 17:37 |
| lxo | I've just had this idea less than an hour ago, I'm still working out the details, so thoughts are welcome | 17:37 |
| danielp3344 | lxo: IMHO people like me with very non formal education are hugely under represented | 17:37 |
| danielp3344 | lkcl: sweet, I'll see if I can be there | 17:37 |
| klys | I'll think it over | 17:37 |
| danielp3344 | cya all later | 17:37 |
| lkcl | danielp3344: self-taught is to be honest exactly what we need. it means "no preconceptions" | 17:37 |
| lkcl | email me luke.leighton@gmail.com | 17:37 |
| lkcl | klys: sure. it's... open discussion. anything you feel like sharing. | 17:38 |
| lxo | I'm also thinking of calling for other GCC developers to participate as mentors/tutors | 17:38 |
| lxo | so that we can accept more applicants | 17:38 |
| lkcl | yeah that'd be a great idea | 17:38 |
| lxo | though others may want to direct their attention to projects other than libre-soc | 17:38 |
| lkcl | libre-soc happens to be one with tax-deductible donations available though :) | 17:39 |
| lkcl | lxo, if you happen to know danielp3344's email address do forward the jitsi link on | 17:39 |
| lxo | I'm also unsure whether to make it a technical, GCC-only thing. I'm considering the possibility of also covering libre philosophy/software ethics/copyleft, and perhaps also neurodiversity | 17:39 |
| lxo | I don't think I do, but danielp3344 is still here, so he'll eventually read this | 17:41 |
| klys | so, in approx. just over five hours from now. how do you link the meeting? | 17:43 |
| lkcl | klys, i can pm you the link - it will be... 24+5 hours (tomorrow UTC 22:00) | 17:46 |
| jn__ | are the libresoc meetings open for outsiders, btw? i think i'd like to listen in | 17:46 |
| lkcl | jn__, yes, of course - it's informal | 17:46 |
| lkcl | it's libresoc / openpower / microwatt / anything-you-like | 17:47 |
| lkcl | they started from the OpenPOWER Virtual Coffee calls that hugh started last year | 17:47 |
| jn__ | great, i'll try to remember the time | 17:47 |
| lkcl | if you email me luke.leighton@gmail.com i can add a calendar invite / reminder | 17:48 |
| lkcl | it's not password protected so please don't publish it widely! | 17:48 |
| jn__ | got it | 17:50 |
| jn__ | mail sent :) | 17:50 |
| lkcl | added you - the 2 reminders are set to go out 1 day before and then a 2nd one 10 mins before | 17:52 |
| programmerjake | :) i kinda have a mostly non-formal education -- >90% of the programming/engineering skills I learned happened outside of formal education ... I started a university degree in electrical engineering/computer engineering but dropped out part way through. I had already written a BASIC-dialect compiler, a 70kloc video game, and designed a really simple cpu before starting college | 18:01 |
| lkcl | and wrote a RISC-V CPU in what, a few hours, yesterday? :) | 18:04 |
| programmerjake | :) | 18:07 |
| jn__ | similar here— i learned to program out of school, then entered university and practically dropped out | 18:08 |
| jn__ | (i'm still enrolled for the formal advantages, because it's cheap here) | 18:08 |
| programmerjake | yup, I got it to run a hello world program after posting the link...idk if any of the unused instructions are correct though | 18:09 |
| lxo | danielp3344, rereading our conversation, I've also realized that "qualify" is not quite what I meant. I don't intend to exclude anyone, but all else being equal, I wish to devote more attention to underprivileged groups so as to try to reduce demographic imbalances | 18:23 |
| lkcl | what lxo is saying is: if you'd like to help with libresoc you're more than welcome :) | 18:28 |
| lkcl | Chips4Makers: install going ok? | 18:29 |
| lxo | lkcl, oh, that's an unrelated given | 18:29 |
| lxo | I was talking specifically about participation in this tutoring program I'm thinking of | 18:30 |
| lkcl | ahh ok | 18:30 |
| lkcl | got it | 18:30 |
| lkcl | Chips4Makers: if you have everything installed in litex, "make run_sim" in the top level soc directory | 18:31 |
| lkcl | eee gods the verilator BIOS load is slow :) | 18:32 |
| lkcl | but it gets there | 18:32 |
| Chips4Makers | '' | 18:36 |
| Chips4Makers | '' | 18:36 |
| Chips4Makers | ['__class__', '__delattr__', '__dict__', '__dir__', '__doc__', '__eq__', '__format__', '__ge__', '__getattribute__', '__gt__', '__hash__', '__init__', '__init_subclass__', '__le__', '__lt__', '__module__', '__ne__', '__new__', '__reduce__', '__reduce_ex__', '__repr__', '__setattr__', '__sizeof__', '__str__', '__subclasshook__', '__weakref__', 'add_op', 'forms', 'instr', 'page', 'pages_written', 'patch_if_needed', 'pprint_o | 18:36 |
| Chips4Makers | ile', 'read_file_for_rewrite', 'write_isa_class', 'write_pysource'] | 18:36 |
| Chips4Makers | Traceback (most recent call last): | 18:36 |
| Chips4Makers | File "/home/verhaegs/eda/Chips4Makers/libre-soc/soc/src/soc/decoder/pseudo/pywriter.py", line 140, in <module> | 18:36 |
| Chips4Makers | if sources[0] == "noall": # don't rewrite all.py | 18:36 |
| Chips4Makers | TypeError: 'dict_keys' object is not subscriptable | 18:36 |
| Chips4Makers | Fail of make run_sim ^ | 18:36 |
| lkcl | Chips4Makers: probably why you should use python 3.7 or 3.8 | 18:41 |
| lkcl | ah 1 sec i think i know what that might be | 18:42 |
| lkcl | nope. | 18:43 |
| lkcl | it'll be because you're using python 3.9 | 18:43 |
| lkcl | oh wait... no, i got it | 18:43 |
| Chips4Makers | solved it: | 18:44 |
| Chips4Makers | diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py | 18:44 |
| Chips4Makers | index bc0f5885..83b9d737 100644 | 18:44 |
| Chips4Makers | --- a/src/soc/decoder/pseudo/pywriter.py | 18:44 |
| Chips4Makers | +++ b/src/soc/decoder/pseudo/pywriter.py | 18:44 |
| Chips4Makers | @@ -133,7 +133,7 @@ if __name__ == '__main__': | 18:44 |
| Chips4Makers | isa = PyISAWriter() | 18:44 |
| Chips4Makers | if len(sys.argv) == 1: # quick way to do it | 18:44 |
| Chips4Makers | print(dir(isa)) | 18:44 |
| Chips4Makers | - sources = isa.page.keys() | 18:44 |
| Chips4Makers | + sources = tuple(isa.page.keys()) | 18:44 |
| Chips4Makers | else: | 18:44 |
| lkcl | yeah that'd do the trick | 18:44 |
| lkcl | the litex thing you'll need to use the older bios isr.c | 18:45 |
| lkcl | although it'd be better to use litex commit 35929c0f8a8f1cc098a6b6ebb569caca8df8c08d for now | 18:45 |
| Chips4Makers | I switched to enjoy-digital litex because I got problem with litedram. | 18:45 |
| lkcl | +++ b/litex/build/io.py | 18:46 |
| lkcl | @@ -64,7 +64,7 @@ class SDRIO(Special): | 18:46 |
| lkcl | 18:46 | |
| lkcl | @staticmethod | 18:46 |
| lkcl | def lower(dr): | 18:46 |
| lkcl | - return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain) | 18:46 |
| lkcl | + return InferedSDRIO(dr.i, dr.o, dr.clk) # dr.clk_domain) | 18:46 |
| lkcl | an error at line 70 of litex/build/io.py by chance? | 18:46 |
| lkcl | i would have to investigate the XICS stuff, gimme a sec to look up the pythondata-microwatt | 18:48 |
| Chips4Makers | Traceback (most recent call last): | 18:49 |
| Chips4Makers | File "/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/./sim.py", line 476, in <module> | 18:49 |
| Chips4Makers | main() | 18:49 |
| Chips4Makers | File "/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/./sim.py", line 465, in main | 18:49 |
| Chips4Makers | soc = LibreSoCSim(cpu=args.cpu, debug=args.debug, variant=args.variant) | 18:49 |
| Chips4Makers | File "/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/./sim.py", line 140, in __init__ | 18:49 |
| Chips4Makers | phy_settings = get_sdram_phy_settings( | 18:49 |
| Chips4Makers | File "/home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/tools/litex_sim.py", line 152, in get_sdram_phy_settings | 18:49 |
| Chips4Makers | return PhySettings( | 18:49 |
| Chips4Makers | TypeError: __init__() got an unexpected keyword argument 'rdcmdphase' | 18:49 |
| lkcl | ngggggh of course there's frickin submodules that are not done as submodules | 18:50 |
| lkcl | in litex they use a "script" | 18:50 |
| lkcl | litedram i am at commit 198bcbab676e2b4065e5b6a7dc8a7733bae8315a | 18:51 |
| lkcl | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/microwatt/irq.h | 18:52 |
| lkcl | ahhh there are the #defines | 18:52 |
| lkcl | 1 sec | 18:52 |
| * lkcl looking up the irq stuff | 18:55 | |
| lkcl | they've switched over to XICS interrupts in the UART stuff | 19:07 |
| lkcl | which may tie problems with the UART to problems with XICS | 19:08 |
| lkcl | i just enabled the IRQ stuff and it doesn't give anything on console | 19:08 |
| lkcl | this is a damn bloody nuisance. | 19:10 |
| lkcl | i'll go through tagging all of the litex sub-repositories | 19:10 |
| lkcl | then sort out a "repro" script for it | 19:11 |
| Chips4Makers | Switched to litedram commit you indicated and I now seem to get further... | 19:13 |
| lkcl | okaaay great | 19:14 |
| lkcl | you can do a "git pull" and "make gitupdate" in soc | 19:14 |
| lkcl | great, because i was about to start tearing my hair out :) | 19:15 |
| lkcl | in pythondata-cpu-microwatt (which _should_ not be needed, | 19:15 |
| lkcl | commit ba76652320e9dc23d9b2c64a62d0a752c870a215 (HEAD, tag: 2020.08, origin/oldmaster) | 19:16 |
| lkcl | i need to document these | 19:16 |
| Chips4Makers | Also had to install pythondata-misc-tapcfg and libjson-c-dev | 19:18 |
| lkcl | ack. the -dev depend i'll add to the auto-scripts | 19:19 |
| lkcl | https://libre-soc.org/HDL_workflow/litex_ls180/ | 19:20 |
| lkcl | done https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=install-hdl-apt-reqs;hb=HEAD | 19:22 |
| Chips4Makers | and verilator... | 19:22 |
| lkcl | ah :) | 19:23 |
| lkcl | ah that needs to be from source | 19:23 |
| lkcl | err there is a debian package | 19:24 |
| lkcl | might work | 19:24 |
| Chips4Makers | symbiflow packages it also with conda, I'm trying that now. | 19:24 |
| lkcl | Package: verilator | 19:25 |
| lkcl | Version: 4.038-1 | 19:25 |
| lkcl | i had built 4.039 from source | 19:25 |
| lkcl | i see no reason why debian/10 verilator shouldn't work? let me check the version | 19:26 |
| lkcl | ok it's bullseye (testing) that has 4.039 | 19:26 |
| Chips4Makers | I have mint and that has version 4.028 | 19:27 |
| lkcl | nice | 19:27 |
| * lkcl need to get up and walk about | 19:29 | |
| Chips4Makers | mkdir -p /home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/obj_dir | 19:33 |
| Chips4Makers | /home/verhaegs/anaconda2/envs/libresoc/bin/x86_64-conda_cos6-linux-gnu-cc -c -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/verhaegs/anaconda2/envs/libresoc/include -Wall -O0 -ggdb -o /home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/obj_dir/modules.o /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/si | 19:33 |
| Chips4Makers | es.c | 19:33 |
| Chips4Makers | /home/verhaegs/anaconda2/envs/libresoc/bin/x86_64-conda_cos6-linux-gnu-cc -c -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/verhaegs/anaconda2/envs/libresoc/include -Wall -O0 -ggdb -o /home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/obj_dir/pads.o /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/c | 19:33 |
| Chips4Makers | /home/verhaegs/anaconda2/envs/libresoc/bin/x86_64-conda_cos6-linux-gnu-cc -c -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/verhaegs/anaconda2/envs/libresoc/include -Wall -O0 -ggdb -o /home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/obj_dir/sim.o /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/co | 19:33 |
| Chips4Makers | /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/sim.c:20:10: fatal error: event2/listener.h: No such file or directory | 19:33 |
| Chips4Makers | #include <event2/listener.h> | 19:33 |
| Chips4Makers | ^~~~~~~~~~~~~~~~~~~ | 19:33 |
| Chips4Makers | compilation terminated. | 19:33 |
| Chips4Makers | make: *** [/home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/Makefile:33: sim.o] Fout 1 | 19:33 |
| Chips4Makers | make: Map '/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware' wordt verlaten | 19:33 |
| lkcl | apt-get install libevent-dev | 19:34 |
| lkcl | dpkg -L libevent-dev | 19:35 |
| lkcl | /usr/include/event2/listener.h | 19:36 |
| lkcl | yep that'll be the one | 19:36 |
| Chips4Makers | Installing symbiflow verilator also installed gcc that did search in /usr/include for includes... | 19:40 |
| Chips4Makers | Switching to OS version of verilator. | 19:40 |
| Chips4Makers | ...did NOT search... | 19:40 |
| lkcl | ehn?? | 19:46 |
| lkcl | i wonder... | 19:46 |
| lkcl | as in: you actually have to work hard to exclude it | 19:48 |
| lkcl | let me see what comes up when i build | 19:48 |
| lkcl | -isystem is what's breaking things | 19:53 |
| lkcl | -isystem /home/verhaegs/anaconda2/envs/libresoc/include -Wall | 19:53 |
| lkcl | that's overriding the default /usr/include for system libraries | 19:53 |
| lkcl | so you'll... ah | 19:53 |
| lkcl | i know | 19:53 |
| lkcl | you'll have to install libevent-dev in *anaconda* | 19:54 |
| lkcl | not in the main system | 19:54 |
| lkcl | that'll do it | 19:54 |
| lkcl | ah ha | 20:15 |
| lkcl | ah hahahahahaa | 20:15 |
| * lkcl laughs manically | 20:15 | |
| lkcl | https://www.eejournal.com/article/heresy-and-horror-ahead-at-intel/?vgo_ee=1acRC9GwO4Iftr6LtLN53zpxdzkQNl9LgdxZ9pnzLRY%3D | 20:15 |
| lkcl | intel's licensing out the x86 ISA... and they expect anyone to take them up on that?? | 20:15 |
| lkcl | ah hahahahaha | 20:15 |
| lkcl | ah ok just its cores, not the ISA :) | 20:16 |
| Chips4Makers | @lkcl: I restarted with a new venv but he seem to have cached a cc somewhere. I already deleted the build directory in libresoc-litex. Do you know where he could have cached that ? | 20:17 |
| Chips4Makers | make MOD=xgmii_ethernet -C xgmii_ethernet -f /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile | 20:17 |
| Chips4Makers | make[2]: Map '/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/modules/xgmii_ethernet' wordt binnengegaan | 20:17 |
| Chips4Makers | /home/verhaegs/anaconda2/envs/libresoc/bin/x86_64-conda_cos6-linux-gnu-cc -c -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/verhaegs/anaconda2/envs/libresoc/include -Wall -O0 -ggdb -Wall -O3 -ggdb -fPIC -Werror -I/home/verhaegs/eda/code/pythondata-misc-tapcfg/pythondata_misc_tapcfg/data/src/include -I/home/verhaegs/eda/Chips4Makers/libre- | 20:17 |
| Chips4Makers | tex/build/sim/core/modules/xgmii_ethernet/../.. -o xgmii_ethernet.o /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c | 20:17 |
| Chips4Makers | make[2]: /home/verhaegs/anaconda2/envs/libresoc/bin/x86_64-conda_cos6-linux-gnu-cc: Opdracht niet gevonden | 20:17 |
| Chips4Makers | make[2]: *** [/home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/modules/rules.mak:18: xgmii_ethernet.o] Fout 127 | 20:17 |
| Chips4Makers | make[2]: Map '/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/modules/xgmii_ethernet' wordt verlaten | 20:17 |
| Chips4Makers | make[1]: *** [/home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/modules/Makefile:9: xgmii_ethernet] Fout 2 | 20:17 |
| Chips4Makers | make[1]: Map '/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware/modules' wordt verlaten | 20:17 |
| Chips4Makers | make: *** [/home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/Makefile:59: modules] Fout 2 | 20:17 |
| Chips4Makers | make: Map '/home/verhaegs/eda/Chips4Makers/libre-soc/libresoc-litex/build/sim/gateware' wordt verlaten | 20:17 |
| lkcl | 1 sec | 20:18 |
| lkcl | you removed the entire build directory there? | 20:18 |
| Chips4Makers | Yes. | 20:18 |
| lkcl | it is symlinks | 20:18 |
| lkcl | not actual files | 20:18 |
| lkcl | so you can see where it is symlinked to | 20:19 |
| lkcl | with ls -altr /home/verhaegs/eda/Chips4Makers/libre-soc/litex/litex/build/sim/core/ | 20:19 |
| lkcl | xgmii_ethernet | 20:20 |
| lkcl | lkcl@fizzy:~/src/libresoc/litex$ | 20:22 |
| lkcl | lkcl@fizzy:~/src/libresoc/litex$ find . -name "xgmii*" | 20:22 |
| lkcl | ./litex/build/sim/core/modules/xgmii_ethernet | 20:22 |
| lkcl | ./litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c | 20:22 |
| lkcl | "litex/build/sim/core/modules/Makefile" | 20:23 |
| lkcl | if it's truly not there then remove it from that file | 20:23 |
| lkcl | you *might* have to remove (or update) the /usr/share/lib/python3.N/dist-packages/litex* stuff | 20:24 |
| lkcl | then re-run python3 setup.py install (or whatever) | 20:25 |
| lkcl | but you have virtual-env so it may be ~/.venv/somewhere/share/lib/blah | 20:25 |
| lkcl | you can probably find out with: | 20:26 |
| lkcl | $ script | 20:26 |
| Chips4Makers | But I started with a fully fresh venv | 20:26 |
| lkcl | interesting. | 20:26 |
| lkcl | well, worth checking with this | 20:26 |
| lkcl | python -v | 20:26 |
| lkcl | >>> import litex (or something inside litex) | 20:27 |
| lkcl | from litex.soc.cores.cpu import CPU | 20:28 |
| lkcl | that would do | 20:28 |
| lkcl | then you can see where "python3 -v" is searching in its import path | 20:29 |
| lkcl | if that *really* doesn't reveal anything: strace -o log.txt -ff python3 | 20:29 |
| lkcl | strace -o log.txt -ff python3 -v | 20:29 |
| lkcl | sorry | 20:29 |
| lkcl | you were very close before, it was installing verilator using conda that caused it to "override" the standard /usr/include with some random location | 20:32 |
| lkcl | relative to the conda directory | 20:32 |
| lkcl | you needed to install libevent-dev *in the conda* installation and it would have worked | 20:32 |
| lkcl | apologies long day have to rest now | 20:33 |
| lkcl | page here | 20:33 |
| lkcl | https://libre-soc.org/HDL_workflow/litex_ls180/ | 20:33 |
| lkcl | with the things we learned/fixed | 20:33 |
| lkcl | back 45mins or so | 20:35 |
| Chips4Makers | Removed verilator and gcc from conda env and then got problems with trying the use of the removed cc. I will likely call it a day very shortly. | 20:35 |
| Chips4Makers | I should have quit shell, it was CC env variable in shell... | 20:40 |
| danielp3344 | lkcl, lxo: my email is danielp3344@tuta.io if you still need it | 20:55 |
| lxo | thanks | 21:25 |
| lkcl | danielp3344, added you | 21:40 |
| lkcl | Chips4Makers: ahh nuts :) | 21:41 |
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