| Chips4Makers | OK, back at it. I am now at stage that sim.py complains about missing libresoc.v file. | 08:15 |
|---|---|---|
| Chips4Makers | ls180soc.py now fails in the following way: | 08:15 |
| Chips4Makers | Traceback (most recent call last): | 08:15 |
| Chips4Makers | File "./ls180soc.py", line 904, in <module> | 08:15 |
| Chips4Makers | main() | 08:15 |
| lkcl | Chips4Makers, great! use "make ls180_verilog" in soc | 10:22 |
| lkcl | that will drop a libresoc.v into the right place | 10:22 |
| lkcl | Chips4Makers: microwatt-litex compiled (and committed) auto-generated verilog. this is not a good idea | 10:38 |
| lkcl | minerva-litex actually calls nmigen to build the auto-generated verilog which adds several *minutes* to the build time | 10:39 |
| lkcl | to save development time i decided to run it manually | 10:40 |
| lkcl | also there are multiple different options | 10:40 |
| lkcl | minerva-litex passes those options through to nmigen building (--disable-cache, etc. etc.) which... yeah | 10:41 |
| lkcl | so just do "make ls180_verilog" in the main soc repo | 10:41 |
| lkcl | that will give 4x SRAM blocks. | 10:41 |
| lkcl | if you don't want 4x 4k SRAM blocks use this | 10:42 |
| lkcl | python3 simple/issuer_verilog.py --debug=jtag --enable-core --enable-pll --enable-xics --disable-svp64 src/soc/litex/florent/libresoc/libresoc.v | 10:42 |
| lkcl | but to be honest, for sim.py, just to get up-and-running, "make ls180_verilog" is fine | 10:43 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=Makefile;h=90d9621938518dd4a0692aedb33624f2898c5985;hb=HEAD#l38 | 10:43 |
| lkcl | line 38 | 10:43 |
| lkcl | whoops git pull on soc, spotted Makefile error | 11:22 |
| Chips4Makers | recompiling yosys now. needed because I switched OS... | 12:13 |
| cesar[m]1 | +# build the litex libresoc SoC without 4k SRAMs | 12:13 |
| cesar[m]1 | +ls180_4ksram_verilog_build: ls180_verilog | 12:13 |
| cesar[m]1 | lkcl: did you mean: +ls180_no_4ksram_verilog_build: ls180_verilog | 12:13 |
| lxo | https://gcc.gnu.org/pipermail/gcc/2021-March/235173.html | 12:25 |
| lkcl | Chips4Makers, ack. we settled on debian, a variant of that should suffice though. or use a chroot | 12:27 |
| lkcl | which is very easy with this: | 12:27 |
| lkcl | https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=mk-deb-chroot;hb=HEAD | 12:27 |
| lkcl | cesar[m]1, let me check | 12:28 |
| lkcl | lxo, nice | 12:28 |
| lkcl | cesar[m]1, yes, without the "no" :) | 12:29 |
| lkcl | cesar[m]1, ah! i will fix that memory port thing, long story | 12:30 |
| lkcl | this is where it needed correcting: | 12:31 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/regfile/regfiles.py;h=fa8994613034a6338f15ed37f9d34e4b2487c09a;hb=HEAD#l86 | 12:31 |
| cesar[m]1 | What I mean, in the Makefile, lines 52 and 56 have the same target. | 12:33 |
| lxo | lkcl, I did not mention the possibility of NLNet funding because I didn't want to make it sound like the program would be able to offer funding for anyone | 12:33 |
| lkcl | makes sense | 12:33 |
| cesar[m]1 | 52: ls180_4ksram_verilog_build: ls180_verilog | 12:34 |
| lkcl | should i do that as a follow-up? or do you want to keep it "clean / clear"? | 12:34 |
| cesar[m]1 | 56: ls180_4ksram_verilog_build: ls180_4k_verilog | 12:34 |
| lkcl | cesar[m]1, yes, https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=434ee06553fc53e46da2282d7017fa68dfa4fb13 | 12:35 |
| lkcl | is that correct? looks it, to me | 12:36 |
| cesar[m]1 | Yes, it was correct, thanks. | 12:39 |
| lkcl | cesar[m]1, thanks for checking | 13:14 |
| lkcl | lxo: btw, you should be aware that talos1.libre-soc.org is not backed up *in any way* and is a sponsored machine | 13:15 |
| lkcl | so the work you've done on there could be irrevocably deleted at any time | 13:15 |
| lkcl | ahh excellent, https://git.libre-soc.org/?p=gcc.git;a=shortlog;h=refs/heads/lxo/WIP-svp64-gcc | 13:16 |
| cesar[m]1 | Checking test_issuer.py with and without "nosvp64" doubles the final testing time... | 13:17 |
| lkcl | sigh yes - i typically only run these: | 13:18 |
| lkcl | python3 simple/test/test_issuer_svp64.py >& /tmp/f | 13:18 |
| lkcl | (and the predication ones) | 13:18 |
| lkcl | python3 simple/test/test_issuer.py nosvp64 >& /tmp/f | 13:18 |
| lkcl | but often first just cut out everything but a few unit tests from it, as a first pass | 13:19 |
| lkcl | hmm i should do that as a command-line, been meaning to for some time | 13:19 |
| Chips4Makers | Make 'ls180_verilog' now completed in soc. sim.py in libresoc-litex still can't find libresoc.v, 'make ls180' or 'make ls1804k` there also fails with wrong number of argument for InferedSDRIO(). | 13:19 |
| Chips4Makers | I want to get the top cell as for yosys with IO cells included. | 13:19 |
| lkcl | Chips4Makers, 1 sec | 13:19 |
| lkcl | --- a/litex/build/io.py | 13:20 |
| lkcl | +++ b/litex/build/io.py | 13:20 |
| lkcl | @@ -64,7 +64,7 @@ class SDRIO(Special): | 13:20 |
| lkcl | 13:20 | |
| lkcl | @staticmethod | 13:20 |
| lkcl | def lower(dr): | 13:20 |
| lkcl | - return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain) | 13:20 |
| lkcl | + return InferedSDRIO(dr.i, dr.o, dr.clk) # dr.clk_domain) | 13:20 |
| lkcl | 13:20 | |
| lkcl | libresoc.v must be in this directory: | 13:21 |
| lkcl | lkcl@fizzy:~/src/libresoc/soc/src/soc/litex/florent$ ls libresoc | 13:21 |
| lkcl | boot-helper.S crt0.S irq.h ls180_pins.py __pycache__ | 13:21 |
| lkcl | core.py __init__.py libresoc.v ls180.py system.h | 13:21 |
| lkcl | i always do the make *in* that directory | 13:21 |
| lkcl | which could be the issue | 13:21 |
| lkcl | https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=libresoc/core.py;h=3340a0c4d13cd65960b80b85eccbea04eb61fda7;hb=47083f3531935d83fd1dfe98faf465cad8804cff#l355 | 13:22 |
| lkcl | line 355 | 13:22 |
| lkcl | no, that should be fine, the path is absolute... ah no it isn't. bleh | 13:23 |
| lkcl | i always add os.path.abpath, but in this case copied cut/paste from litex | 13:23 |
| lkcl | Chips4Makers: to make libresoc.v you must run, in the main soc repo top-level: "make ls180_verilog" | 13:26 |
| lkcl | it is deliberately not done every time under litex, because it takes quite some time | 13:26 |
| Chips4Makers | So I have to manually copy libresoc.v over from soc/.../florent/... to libresoc-litex/libresoc ? | 13:29 |
| lxo | lkcl, I got a local copy too | 13:29 |
| lxo | thanks for the info | 13:29 |
| lkcl | soc/..../florent is a git submodule | 13:30 |
| lkcl | it was updated by "make gitupdate" | 13:30 |
| lkcl | so you do not need a second copy libresoc-litex/libresoc | 13:31 |
| lkcl | if however you are using a second copy, libresoc-litex/libresoc | 13:31 |
| lkcl | then yes, you will need to adjust the instructions above | 13:31 |
| Chips4Makers | The only libresoc.v I currently have is: | 13:31 |
| Chips4Makers | (libresoc) verhaegs@hpdc7800:~/eda/Chips4Makers/libre-soc/soc$ find . -name libresoc.v | 13:31 |
| Chips4Makers | ./src/soc/litex/florent/libresoc/libresoc.v | 13:31 |
| lkcl | ok then cd ./src/soc/litex/florent | 13:31 |
| lkcl | and do "make ls180" there | 13:31 |
| lkcl | rather than | 13:32 |
| lkcl | cd ./src/libresoc-litex | 13:32 |
| lkcl | and doing "make ls180 there" (this will fail unless you have copied libresoc.v to it) | 13:32 |
| lkcl | i am updating the wiki page instructions for you, 1 sec | 13:33 |
| Chips4Makers | cp build/ls180/gateware/mem_2.init . | 13:33 |
| Chips4Makers | cp: kan status van 'build/ls180/gateware/mem_2.init' niet opvragen: Bestand of map bestaat niet | 13:33 |
| Chips4Makers | make ls1804k seems to go further | 13:34 |
| lkcl | Chips4Makers, run "make gitupdate" i fixed that an hour ago | 13:34 |
| Chips4Makers | Did make gitupdate half a minute ago... | 13:35 |
| lkcl | sorry, i forgot to push :) | 13:35 |
| lkcl | https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=89b40eec31e22bb611087683f17dc5b7041ff8fa | 13:36 |
| lkcl | https://libre-soc.org/HDL_workflow/litex_ls180/ | 13:38 |
| Chips4Makers | So ls180.il contains the full design for synthesis and P&R. Right ? | 13:40 |
| lkcl | Chips4Makers, yes | 13:40 |
| lkcl | and because it's in ilang it doesn't need those mem.init files | 13:40 |
| lkcl | verilog _would_ need them, even though they're empty (sigh) | 13:41 |
| lkcl | i will just add the process for ls180 4k sram to the wiki page as well 1 sec | 13:41 |
| lkcl | https://libre-soc.org/HDL_workflow/litex_ls180/ | 13:46 |
| lkcl | note that you *MIGHT* not need the variant of yosys checkout (in the coriolis2 chroot) | 13:47 |
| lkcl | if building succeeds using the latest master yosys inside the chroot please do let me know | 13:48 |
| lkcl | cesar[m]1, you can use the detection of the PriorityEncoder.n being high if you choose | 13:51 |
| lkcl | https://github.com/m-labs/nmigen/blob/4a59d5d1797c3c39b8f08d0ed9e2abbf71739cda/nmigen/lib/coding.py#L56 | 13:51 |
| lkcl | if using the guard bit i recommend using Cat(self.srcmask, Const(1,1)) so that it knows the exact length | 13:53 |
| lkcl | but it is also nice, "with m.If(src_delta.n): # skip everything, all zero" | 13:54 |
| cesar[m]1 | Sure. I just wanted to avoid adding a special case for it. | 13:55 |
| lkcl | ahh :) | 13:55 |
| lkcl | makes perfect sense | 13:55 |
| lkcl | Chips4Makers, how you getting on, i just need to get up and move about, get tea | 13:56 |
| Chips4Makers | Will be busy for a while, | 14:01 |
| lkcl | cesar[m]1, can i recommend not trying to use srcmask and dstmask as state-dependent variables? for re-entrant case (return from interrupt) it will make things difficult | 14:02 |
| lkcl | Chips4Makers: ack | 14:02 |
| lkcl | cesar[m]1, you can always use srcmask.bit_select(src_delta), this will detect the relevant bit in all circumstances | 14:03 |
| lkcl | including on re-entrant | 14:03 |
| Chips4Makers | One thing: IO cells are not in this netlist yet. They will be added by Coriolis IO ring script. Correct ? | 14:03 |
| cesar[m]1 | My plan was to initialize srcmask as (srcmask << srcstep) at predication fetch. | 14:04 |
| cesar[m]1 | srcmask = (initial srcmask >> initial srcstep) | 14:05 |
| cesar[m]1 | Count leading zeros won't work, unless I shift out the previously used srcstep bits first. I guess I could do that. | 14:11 |
| lkcl | Chips4Makers, correct. they do indeed get added by corona.py etc. | 14:13 |
| lkcl | cumulus/src/plugins/alpha/chip/corona.py | 14:13 |
| lkcl | cumulus/src/plugins/alpha/block/iospecs.py | 14:13 |
| lkcl | cesar[m]1: yes, it can be done by doing: | 14:14 |
| lkcl | ((1<<initial_srcstep)-1) | 14:15 |
| lkcl | AND that out of srcmask :) | 14:15 |
| lkcl | the nice thing is, that calculation can be done all in one step, then | 14:15 |
| cesar[m]1 | The SVP64 Assembler is choking on "sv.add/m=r3 1.v, 5.v, 9.v" | 14:15 |
| lkcl | cesar[m]1, 1 sec | 14:16 |
| cesar[m]1 | AssertionError: source-mask can only be specified on Twin-predicate ops | 14:16 |
| lkcl | let me check it | 14:16 |
| cesar[m]1 | Sure. | 14:16 |
| lkcl | blegh :) | 14:17 |
| lkcl | single-predication | 14:17 |
| * lkcl just deleting that Assert :) | 14:18 | |
| lkcl | i have a better way | 14:19 |
| lkcl | cesar[m]1, can you add an expected VEXPAND example to decoder/isa/test_caller_svp64_predication.py? | 14:21 |
| lkcl | no need to have "skip" on it | 14:21 |
| lkcl | unit tests are supposed to fail if they are supposed to fail | 14:21 |
| lkcl | the only reason for adding "skip" is if they cause damage, or are other unmitigated disasters | 14:22 |
| lkcl | cesar[m]1, sorted - https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=d8948f6d04062b03f87352756e3357c64ceb2494 | 14:24 |
| * lkcl out for a walk | 14:25 | |
| cesar[m]1 | Sure, will do. | 14:30 |
| cesar[m]1 | Could also clear the mask bits like this: new_srcmask.eq(old_srcmask & ((-1) << old_srcstep)). | 14:44 |
| cesar[m]1 | Point is, I suspect we could "count leading zeros" and "shift out leading zero bits" in the same step, in hardware. | 14:46 |
| lkcl | cesar[m]1, oh yes, of course | 14:53 |
| programmerjake | lkcl double checking: which meeting was rescheduled? icr | 21:12 |
| *** segher_ is now known as segher | 21:38 | |
| lkcl | none of them... yet. however the tuesday one is fixed at *UTC 2200* | 22:03 |
| lkcl | which is in 1 hour | 22:03 |
| programmerjake | k, thx | 22:03 |
| lkcl | still have yet to hear from paul, mikey, anton, about what time's best suited for them, for the wednesday bi-weekly | 22:05 |
| lkcl | the TZ shift in AUS occurs April 4th https://www.timeanddate.com/time/change/australia | 22:06 |
| programmerjake | oh, on my brother's birthday! | 22:08 |
| lkcl | :) | 22:09 |
| lkcl | meeting 15 mins | 22:46 |
| lkcl | cesar[m]1, ^ | 22:46 |
| lkcl | lxo, ^ | 22:46 |
| lkcl | klys, ^ | 22:46 |
| lkcl | danielp3344, ^ | 22:46 |
| lkcl | jn__, ^ | 22:46 |
| klys | ahh | 22:47 |
| klys | thanks | 22:47 |
| danielp3344 | I'm here :P | 22:51 |
| * danielp3344 just needs to find a microphone... | 22:51 | |
| * lx0 seems to have messed up with timezone calculations. wasn't the meeting moved to 2300UTC? | 23:57 | |
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