Tuesday, 2021-03-30

Chips4MakersOK, back at it. I am now at stage that sim.py complains about missing libresoc.v file.08:15
Chips4Makersls180soc.py now fails in the following way:08:15
Chips4MakersTraceback (most recent call last):08:15
Chips4Makers  File "./ls180soc.py", line 904, in <module>08:15
Chips4Makers    main()08:15
lkclChips4Makers, great! use "make ls180_verilog" in soc10:22
lkclthat will drop a libresoc.v into the right place10:22
lkclChips4Makers: microwatt-litex compiled (and committed) auto-generated verilog. this is not a good idea10:38
lkclminerva-litex actually calls nmigen to build the auto-generated verilog which adds several *minutes* to the build time10:39
lkclto save development time i decided to run it manually10:40
lkclalso there are multiple different options10:40
lkclminerva-litex passes those options through to nmigen building (--disable-cache, etc. etc.) which... yeah10:41
lkclso just do "make ls180_verilog" in the main soc repo10:41
lkclthat will give 4x SRAM blocks.10:41
lkclif you don't want 4x 4k SRAM blocks use this10:42
lkclpython3 simple/issuer_verilog.py --debug=jtag --enable-core --enable-pll --enable-xics  --disable-svp64  src/soc/litex/florent/libresoc/libresoc.v10:42
lkclbut to be honest, for sim.py, just to get up-and-running, "make ls180_verilog" is fine10:43
lkclline 3810:43
lkclwhoops git pull on soc, spotted Makefile error11:22
Chips4Makersrecompiling yosys now. needed because I switched OS...12:13
cesar[m]1+# build the litex libresoc SoC without 4k SRAMs12:13
cesar[m]1+ls180_4ksram_verilog_build: ls180_verilog12:13
cesar[m]1lkcl: did you mean: +ls180_no_4ksram_verilog_build: ls180_verilog12:13
lkclChips4Makers, ack. we settled on debian, a variant of that should suffice though. or use a chroot12:27
lkclwhich is very easy with this:12:27
lkclcesar[m]1, let me check12:28
lkcllxo, nice12:28
lkclcesar[m]1, yes, without the "no" :)12:29
lkclcesar[m]1, ah! i will fix that memory port thing, long story12:30
lkclthis is where it needed correcting:12:31
cesar[m]1What I mean, in the Makefile, lines 52 and 56 have the same target.12:33
lxolkcl, I did not mention the possibility of NLNet funding because I didn't want to make it sound like the program would be able to offer funding for anyone12:33
lkclmakes sense12:33
cesar[m]152: ls180_4ksram_verilog_build: ls180_verilog12:34
lkclshould i do that as a follow-up? or do you want to keep it "clean / clear"?12:34
cesar[m]156: ls180_4ksram_verilog_build: ls180_4k_verilog12:34
lkclcesar[m]1, yes, https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=434ee06553fc53e46da2282d7017fa68dfa4fb1312:35
lkclis that correct? looks it, to me12:36
cesar[m]1Yes, it was correct, thanks.12:39
lkclcesar[m]1, thanks for checking13:14
lkcllxo: btw, you should be aware that talos1.libre-soc.org is not backed up *in any way* and is a sponsored machine13:15
lkclso the work you've done on there could be irrevocably deleted at any time13:15
lkclahh excellent, https://git.libre-soc.org/?p=gcc.git;a=shortlog;h=refs/heads/lxo/WIP-svp64-gcc13:16
cesar[m]1Checking test_issuer.py with and without "nosvp64" doubles the final testing time...13:17
lkclsigh yes - i typically only run these:13:18
lkclpython3 simple/test/test_issuer_svp64.py >& /tmp/f13:18
lkcl(and the predication ones)13:18
lkclpython3 simple/test/test_issuer.py nosvp64 >& /tmp/f13:18
lkclbut often first just cut out everything but a few unit tests from it, as a first pass13:19
lkclhmm i should do that as a command-line, been meaning to for some time13:19
Chips4MakersMake 'ls180_verilog' now completed in soc. sim.py in libresoc-litex still can't find libresoc.v, 'make ls180' or 'make ls1804k` there also fails with wrong number of argument for InferedSDRIO().13:19
Chips4MakersI want to get the top cell as for yosys with IO cells included.13:19
lkclChips4Makers, 1 sec13:19
lkcl--- a/litex/build/io.py13:20
lkcl+++ b/litex/build/io.py13:20
lkcl@@ -64,7 +64,7 @@ class SDRIO(Special):13:20
lkcl     @staticmethod13:20
lkcl     def lower(dr):13:20
lkcl-        return InferedSDRIO(dr.i, dr.o, dr.clk, dr.clk_domain)13:20
lkcl+        return InferedSDRIO(dr.i, dr.o, dr.clk) # dr.clk_domain)13:20
lkcllibresoc.v must be in this directory:13:21
lkcllkcl@fizzy:~/src/libresoc/soc/src/soc/litex/florent$ ls libresoc13:21
lkclboot-helper.S  crt0.S       irq.h       ls180_pins.py  __pycache__13:21
lkclcore.py        __init__.py  libresoc.v  ls180.py       system.h13:21
lkcli always do the make *in* that directory13:21
lkclwhich could be the issue13:21
lkclline 35513:22
lkclno, that should be fine, the path is absolute... ah no it isn't.  bleh13:23
lkcli always add os.path.abpath, but in this case copied cut/paste from litex13:23
lkclChips4Makers: to make libresoc.v you must run, in the main soc repo top-level: "make ls180_verilog"13:26
lkclit is deliberately not done every time under litex, because it takes quite some time13:26
Chips4MakersSo I have to manually copy libresoc.v over from soc/.../florent/... to libresoc-litex/libresoc ?13:29
lxolkcl, I got a local copy too13:29
lxothanks for the info13:29
lkclsoc/..../florent is a git submodule13:30
lkclit was updated by "make gitupdate"13:30
lkclso you do not need a second copy libresoc-litex/libresoc13:31
lkclif however you are using a second copy, libresoc-litex/libresoc13:31
lkclthen yes, you will need to adjust the instructions above13:31
Chips4MakersThe only libresoc.v I currently have is:13:31
Chips4Makers(libresoc) verhaegs@hpdc7800:~/eda/Chips4Makers/libre-soc/soc$ find . -name libresoc.v13:31
lkclok then cd ./src/soc/litex/florent13:31
lkcland do "make ls180" there13:31
lkclrather than13:32
lkclcd ./src/libresoc-litex13:32
lkcland doing "make ls180 there" (this will fail unless you have copied libresoc.v to it)13:32
lkcli am updating the wiki page instructions for you, 1 sec13:33
Chips4Makerscp build/ls180/gateware/mem_2.init .13:33
Chips4Makerscp: kan status van 'build/ls180/gateware/mem_2.init' niet opvragen: Bestand of map bestaat niet13:33
Chips4Makersmake ls1804k seems to go further13:34
lkclChips4Makers, run "make gitupdate" i fixed that an hour ago13:34
Chips4MakersDid make gitupdate half a minute ago...13:35
lkclsorry, i forgot to push :)13:35
Chips4MakersSo ls180.il contains the full design for synthesis and P&R. Right ?13:40
lkclChips4Makers, yes13:40
lkcland because it's in ilang it doesn't need those mem.init files13:40
lkclverilog _would_ need them, even though they're empty (sigh)13:41
lkcli will just add the process for ls180 4k sram to the wiki page as well 1 sec13:41
lkclnote that you *MIGHT* not need the variant of yosys checkout (in the coriolis2 chroot)13:47
lkclif building succeeds using the latest master yosys inside the chroot please do let me know13:48
lkclcesar[m]1, you can use the detection of the PriorityEncoder.n being high if you choose13:51
lkclif using the guard bit i recommend using Cat(self.srcmask, Const(1,1)) so that it knows the exact length13:53
lkclbut it is also nice, "with m.If(src_delta.n): # skip everything, all zero"13:54
cesar[m]1Sure. I just wanted to avoid adding a special case for it.13:55
lkclahh :)13:55
lkclmakes perfect sense13:55
lkclChips4Makers, how you getting on, i just need to get up and move about, get tea13:56
Chips4MakersWill be busy for a while,14:01
lkclcesar[m]1, can i recommend not trying to use srcmask and dstmask as state-dependent variables? for re-entrant case (return from interrupt) it will make things difficult14:02
lkclChips4Makers: ack14:02
lkclcesar[m]1, you can always use srcmask.bit_select(src_delta), this will detect the relevant bit in all circumstances14:03
lkclincluding on re-entrant14:03
Chips4MakersOne thing: IO cells are not in this netlist yet. They will be added by Coriolis IO ring script. Correct ?14:03
cesar[m]1My plan was to initialize srcmask as (srcmask << srcstep) at predication fetch.14:04
cesar[m]1srcmask = (initial srcmask >> initial srcstep)14:05
cesar[m]1Count leading zeros won't work, unless I shift out the previously used srcstep bits first. I guess I could do that.14:11
lkclChips4Makers, correct.  they do indeed get added by corona.py etc.14:13
lkclcesar[m]1: yes, it can be done by doing:14:14
lkclAND that out of srcmask :)14:15
lkclthe nice thing is, that calculation can be done all in one step, then14:15
cesar[m]1The SVP64 Assembler is choking on "sv.add/m=r3 1.v, 5.v, 9.v"14:15
lkclcesar[m]1, 1 sec14:16
cesar[m]1AssertionError: source-mask can only be specified on Twin-predicate ops14:16
lkcllet me check it14:16
lkclblegh :)14:17
* lkcl just deleting that Assert :)14:18
lkcli have a better way14:19
lkclcesar[m]1, can you add an expected VEXPAND example to decoder/isa/test_caller_svp64_predication.py?14:21
lkclno need to have "skip" on it14:21
lkclunit tests are supposed to fail if they are supposed to fail14:21
lkclthe only reason for adding "skip" is if they cause damage, or are other unmitigated disasters14:22
lkclcesar[m]1, sorted - https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=d8948f6d04062b03f87352756e3357c64ceb249414:24
* lkcl out for a walk14:25
cesar[m]1Sure, will do.14:30
cesar[m]1Could also clear the mask bits like this: new_srcmask.eq(old_srcmask & ((-1) << old_srcstep)).14:44
cesar[m]1Point is, I suspect we could "count leading zeros" and "shift out leading zero bits" in the same step, in hardware.14:46
lkclcesar[m]1, oh yes, of course14:53
programmerjakelkcl double checking: which meeting was rescheduled? icr21:12
*** segher_ is now known as segher21:38
lkclnone of them... yet.  however the tuesday one is fixed at *UTC 2200*22:03
lkclwhich is in 1 hour22:03
programmerjakek, thx22:03
lkclstill have yet to hear from paul, mikey, anton, about what time's best suited for them, for the wednesday bi-weekly22:05
lkclthe TZ shift in AUS occurs April 4th https://www.timeanddate.com/time/change/australia22:06
programmerjakeoh, on my brother's birthday!22:08
lkclmeeting 15 mins22:46
lkclcesar[m]1, ^22:46
lkcllxo, ^22:46
lkclklys, ^22:46
lkcldanielp3344, ^22:46
lkcljn__, ^22:46
danielp3344I'm here :P22:51
* danielp3344 just needs to find a microphone...22:51
* lx0 seems to have messed up with timezone calculations. wasn't the meeting moved to 2300UTC?23:57

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