| Veera[m] | Hi | 05:45 |
|---|---|---|
| *** ghostmansd-pc <ghostmansd-pc!~kvirc@broadband-188-32-220-29.ip.moscow.rt.ru> has left #libre-soc | 12:11 | |
| ghostmansd | lkcl: https://bugs.libre-soc.org/show_bug.cgi?id=712#c5 | 12:12 |
| ghostmansd | Please, let me know if you have ideas how to prefix pyfnwriter-generated calls; I'd like the generator to be as restrictive as possible, exactly like I did with "fixed" helpers. That is, I'd like to avoid prefixing everything I meet with "self." prefix. | 12:14 |
| ghostmansd | However, for now this seems to be the simplest option. | 12:15 |
| ghostmansd | Especially given that we tend to invoke pywriter/pyfnwriter code manually, so supplying a new pywriter input / pyfnwriter output is kinda verbose. | 12:16 |
| lkcl | v. tired | 12:50 |
| lkcl | do best you can | 12:50 |
| lkcl | add DPD_TO_BCD etc to list which puts "self." in front | 12:53 |
| lkcl | make pyfnwriter generate class | 12:53 |
| lkcl | inherit class in caller.py | 12:53 |
| lkcl | like pywriter all.py | 12:54 |
| lkcl | fnall.py | 12:54 |
| ghostmansd[m] | lkcl: that's OK, take your time and have a rest! I'll handle it | 14:25 |
| ghostmansd | for blech in ['NIA', 'end_loop'] | 15:49 |
| ghostmansd | couldn't resist to laugh :-D | 15:49 |
| ghostmansd | if blech in pycode: # HACK - TODO fix | 15:50 |
| ghostmansd | lkcl, I must stress: I _really_ like the parser | 15:50 |
| ghostmansd | each encounter is an entertainment | 15:50 |
| *** kylel1 is now known as kylel | 16:10 | |
| lkcl | well, laughing at how awful it is is better than crying | 17:14 |
| ghostmansd | I didn't mean awful | 18:41 |
| ghostmansd | I saw lots of awful code | 18:41 |
| ghostmansd | this one isn't as awful as you might think | 18:41 |
| Las[m] | So I'm trying to program my ECP5 with Libre-SOC, and I get this error: https://gist.github.com/L-as/f406004e3cd6850694a95e3c3c997c7f | 19:36 |
| Las[m] | what does this mean? | 19:36 |
| Las[m] | Which error is fatal? | 19:37 |
| Las[m] | I'm not even sure what program it is that is failing specifically. | 19:47 |
| lkcl | notice how the "identifier" is mutlipled by 2? | 19:54 |
| lkcl | 0x222NNN | 19:54 |
| lkcl | intsead of 0x111NNNN | 19:54 |
| lkcl | that's a bug in either openocd or in the FT232 firmware to which openocd is connecting on the VERSA_ECP5 | 19:54 |
| lkcl | it hasn't even got to the point of uploading the bitstream, at all | 19:55 |
| lkcl | try the debian/10 version of openocd | 19:56 |
| lkcl | openocd --version | 19:56 |
| lkcl | Open On-Chip Debugger 0.10.0+dev-00198-g35eed36f (2018-11-17-00:51) | 19:56 |
| lkcl | Licensed under GNU GPL v2 | 19:56 |
| lkcl | For bug reports, read | 19:56 |
| lkcl | http://openocd.org/doc/doxygen/bugs.html | 19:56 |
| Las[m] | Thanks, I'll try that. | 20:21 |
| cesar | The unexpected device found in the JTAG chain at line 68 seems suspicious. | 20:35 |
| Las[m] | I switched to openocd 0.10 and the error says that it read 0x44810c01 now... | 20:36 |
| Las[m] | Why is backward compatibility not a thing for FPGA tooling | 20:36 |
| Las[m] | Does openocd depend on prjtrellis or similar? | 20:37 |
| cesar | Did you power off the board before retrying? | 20:38 |
| Las[m] | No, I didn't | 20:39 |
| Las[m] | Do I need to do that? | 20:39 |
| Las[m] | I am very new to FPGAs | 20:39 |
| cesar | JTAG is based on a shift-register. Maybe something was left from your earlier attempt. | 20:41 |
| Las[m] | I don't think it's using JTAG; I haven't connected anything to the JTAG interface | 20:41 |
| cesar | The USB cable leads to a USB-to-JTAG converter on the board itself. | 20:42 |
| cesar | Anyway, to see if the error is repeatable and reproducible, better to retry from the beginning, with the board off. | 20:44 |
| Las[m] | Will do, I assume I just pull the plug out? | 20:46 |
| cesar | I suppose so. Better disconnect the USB as well, and connect it again AFTER turning it on. | 20:49 |
| cesar | lkcl: Did you by any chance changed the jumpers on J50, on your board, to remove an "ispCLOCK" device from the scan chain? If so, Las should do the same. | 20:57 |
| cesar | See J50 settings on https://www.latticesemi.com/view_document?document_id=50996, pg 19. | 20:58 |
| lkcl | JTAG is a Finite State Machine | 21:03 |
| lkcl | also, FT232 / FT2232 USB-UARTs are susceptible to "Ground Loops" | 21:03 |
| lkcl | if you are operating without a proper earthed Power Supply (very common in Europe) by only using a 2-pin power block, or if using a laptop whose PSU does not have an earth pin, you get fluctuations in power | 21:04 |
| lkcl | and USB-UARTs only operate with "pull-down" (floating 3.3v) | 21:05 |
| lkcl | they're very cheap | 21:05 |
| lkcl | so you could easily be "spiking" the USB-UART and not know it | 21:05 |
| lkcl | because the VERSA_ECP5 is running from a 12v PSU | 21:06 |
| Las[m] | ah | 21:06 |
| lkcl | and there's a loop which goes: | 21:06 |
| lkcl | * USB earth line | 21:06 |
| lkcl | * into VERSA ECP5 | 21:06 |
| lkcl | * down the 12v PSU | 21:06 |
| lkcl | * through the power socket | 21:06 |
| lkcl | * through the mains earth | 21:06 |
| lkcl | * through to the Laptop PSU | 21:07 |
| lkcl | * through to the DC supply of the laptop PSU | 21:07 |
| lkcl | * into the PCB of the laptop | 21:07 |
| lkcl | * back out to the USB GND earth line | 21:07 |
| lkcl | all of which is totally susceptible to 110/240 volt AC Mains "hum" | 21:07 |
| lkcl | and just general resistance | 21:07 |
| lkcl | you can *MAYBE* "solve" this problem by disconnecting the laptop from its PSU | 21:08 |
| Las[m] | so could this becausing it? | 21:08 |
| lkcl | or | 21:08 |
| lkcl | get a powered USB Hub | 21:08 |
| lkcl | and connect the USB-UART into the hub | 21:08 |
| lkcl | if you constantly get errors (that report of what "ID" is) is completely different each time, it's likely | 21:09 |
| lkcl | cesar: i honestly can't remember | 21:09 |
| lkcl | i have pins 1-2 with a jumper | 21:10 |
| cesar | Could you look at J50 on your board? It should be near the FTDI chip. | 21:10 |
| lkcl | and 3-5 connected with another jumper | 21:10 |
| Las[m] | It doesn't seem to be completely different every time. | 21:10 |
| lkcl | 6-4 are NOT connected | 21:11 |
| lkcl | ok that's a good sign | 21:11 |
| lkcl | check J50. | 21:11 |
| cesar | Las: Could you check your J50 to see if it matches? | 21:11 |
| Las[m] | Restarting, it says "READ = 0x2224086" again | 21:11 |
| Las[m] | I assume it's written on the board, where that is? | 21:11 |
| lkcl | btw, you have the PCB on a wooden desk? | 21:11 |
| Las[m] | I do | 21:11 |
| Las[m] | It's on the bubblwrapping itcame with though | 21:12 |
| Las[m] | Between the wood and it | 21:12 |
| lkcl | not "a piece of static-ridden carpet" | 21:12 |
| lkcl | about 50 mm to the left of the USB connector | 21:12 |
| lkcl | right sorry | 21:12 |
| lkcl | USB connector | 21:12 |
| lkcl | 25 mm to the right is the FT2322 ASIC (48 QFP i think) | 21:13 |
| lkcl | 25 mm further to the right is J50. look closely at the PCB "silk screen" (white writing) | 21:13 |
| lkcl | pins 1 2 5 and 6 are all marked, writing appx 2mm high | 21:13 |
| Las[m] | Not sure how this will look on the IRC side | 21:14 |
| * Las[m] uploaded an image: (3061KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/yKGOiNMMxEfpodGRHpiuyWln/IMG_20210926_194826.jpg > | 21:14 | |
| Las[m] | I sent a picture of it | 21:14 |
| lkcl | yeah please don't use IRC for uploading of images | 21:14 |
| lkcl | just because matrix can do it doesn't mean IRC can | 21:14 |
| Las[m] | What do you see? Nothing? | 21:14 |
| lkcl | Las[m] uploaded an image: (3061KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/yKGOiNMMxEfpodGRHpiuyWln/IMG_20210926_194826.jpg > | 21:14 |
| lkcl | <Las[m]> I sent a picture of it | 21:14 |
| Las[m] | Oh that's nice | 21:15 |
| lkcl | turn through 90 degrees | 21:15 |
| lkcl | 50 mm in from the USB connector | 21:15 |
| lkcl | in writing 2mm high, look for white writing "J50" | 21:15 |
| lkcl | disconnect all power | 21:16 |
| lkcl | disconnect all cables | 21:16 |
| lkcl | make absolutely certain there is no power | 21:16 |
| lkcl | DO NOT touch the PCB itself | 21:16 |
| lkcl | ONLY handle it by the edges | 21:16 |
| lkcl | and certainly do not touch the gold connector with your fingers | 21:16 |
| lkcl | (the PCIe connector) | 21:16 |
| Las[m] | I feel blind | 21:17 |
| Las[m] | oh I can see jtag act | 21:18 |
| Las[m] | not j50 | 21:18 |
| cesar | From the photo, Las seems to have J50 in the factory condition: 1-2, 3-4, 5-6. | 21:18 |
| lkcl | cesar, ah good, you were able to make it out | 21:19 |
| lkcl | this is very easy, Las, but you need to stop thinking in terms of "it's a monolithic object / black box, it Should Just Work" | 21:19 |
| lkcl | i'm feeling your hesitance, let's walk you through it | 21:20 |
| Las[m] | yeah | 21:20 |
| lkcl | https://ftp.libre-soc.org/2021-09-26_21-18.png | 21:20 |
| lkcl | u | 21:20 |
| Las[m] | ah | 21:21 |
| lkcl | if you have a magnifying glass or a bright light (or both) it will help | 21:21 |
| lkcl | now re-read what i wrote about the jumpers... 1 sec... | 21:21 |
| Las[m] | I was using a bright light, but didn't notice it because it was shadowing it | 21:21 |
| Las[m] | should have thought about that | 21:21 |
| lkcl | https://libre-soc.org/irclog/%23libre-soc.2021-09-26.log.html#t2021-09-26T21:10:26 | 21:21 |
| lkcl | remove the jumper between pin 6 and 4. put it back "hanging" on either pin 6 or pin 4 so you do not lose it | 21:22 |
| lkcl | (one of the worst bloody things in the world, having $200-$1000 equipment that you can't use because of a missing $0.02 jumper) | 21:22 |
| Las[m] | it seems to be that the jumper is between 6 and 5 | 21:23 |
| Las[m] | 3-4 and 1-2 | 21:23 |
| lkcl | urrr lovely | 21:23 |
| lkcl | ok | 21:23 |
| lkcl | turn them round so they're in the configuration i described | 21:24 |
| lkcl | https://libre-soc.org/irclog/%23libre-soc.2021-09-26.log.html#t2021-09-26T21:10:26 | 21:24 |
| Las[m] | yeah | 21:24 |
| Las[m] | done | 21:25 |
| Las[m] | Should this fix it? | 21:25 |
| lkcl | yes | 21:26 |
| lkcl | but do NOT power up yet | 21:26 |
| lkcl | i am just checking the schematics for the ECP5 | 21:26 |
| lkcl | which you should also check for yourself | 21:26 |
| lkcl | ALWAYS DOUBLE CHECK | 21:26 |
| Las[m] | Thanks | 21:27 |
| lkcl | mistakes are costly with electronics | 21:27 |
| Las[m] | I'll have to find them first | 21:27 |
| Las[m] | I don't think I got one in the package | 21:27 |
| lkcl | https://ftp.libre-soc.org/FPGA-EB-02021-2-3-ECP5-Versa-Development-Board.pdf | 21:27 |
| lkcl | see page 19 of that PDF | 21:27 |
| lkcl | turn it clockwise through 90 degrees | 21:28 |
| lkcl | then zoom in on Quadrant 1-C | 21:29 |
| lkcl | (or, half-way between 1-C and 1-D) | 21:29 |
| lkcl | 1-C and 1-B sorry | 21:29 |
| lkcl | https://ftp.libre-soc.org/2021-09-26_21-28.png | 21:29 |
| Las[m] | Thanks, found it myself a few moments ago too | 21:30 |
| lkcl | notice how it says, ispClock TD*in* is on pin 4 and ispClock TD*out* is on pin 6? | 21:30 |
| Las[m] | Ah, makes sense then | 21:30 |
| lkcl | yes. | 21:30 |
| lkcl | openocd clearly wants to be "in control" of the JTAG clock speed | 21:31 |
| lkcl | rather than syncing to an external one | 21:31 |
| lkcl | so now, as long as you have triple-checked the J50 jumper setting, you should be good to go. | 21:31 |
| lkcl | make sure *absolutely no metal* is anywhere near the board | 21:31 |
| lkcl | no other cables | 21:32 |
| lkcl | and that it's either directly on bare wood | 21:32 |
| lkcl | or on the anti-static bag | 21:32 |
| lkcl | that plastic thing with bubble-wrap is **NOT** a good surface to put it onto | 21:32 |
| lkcl | it can transmit ESD shock @ 2000 to 5000 v at tiny currents (micro-amps) directly into the electronics, and destroy it | 21:33 |
| lkcl | so put it on the silver-looking anti-static bag | 21:33 |
| lkcl | or directly onto the wood | 21:33 |
| lkcl | only when you are ready, and everything is totally clear, no possibility of loose cables with metal connectors moving about on the desk and shorting against components | 21:34 |
| lkcl | 1) entirely disconnect the USB cable | 21:34 |
| lkcl | 2) entirely disconnect the 12v PSU (or better, if it has a switch, flick the switch so that it is "off") | 21:35 |
| Las[m] | I'll put it on the wood, because I don't think an anti-static bag came with it | 21:35 |
| lkcl | 3) **WITHOUT** touching **ANY** part of the PCB (hold on to the Ethernet cables or put the PCB temporarily back into the silver anti-static bag) | 21:35 |
| lkcl | argh that's really bad | 21:36 |
| lkcl | that's a serious mistake made by the supplier | 21:36 |
| lkcl | ok grab it by the metal Ethernet and carefully plug in the USB connector | 21:36 |
| lkcl | or, hold it by its top and bottom edges | 21:37 |
| lkcl | WITHOUT touching components | 21:37 |
| Las[m] | Yeah I've been holding it carefully until now thankfully | 21:37 |
| lkcl | 4) very carefully - DOUBLE CHECKING that the PSU is either unplugged (or better switched off) | 21:37 |
| lkcl | plug in the 12v PSU | 21:37 |
| Las[m] | There was a miscommunication between me and Restivo which made me think it was the best thing to put it on... | 21:37 |
| lkcl | the 5.1 mm jack needs quite a bit of force | 21:38 |
| lkcl | then, plug in the *other* end of the USB cable | 21:38 |
| lkcl | this should actually power up the FT2322 but it's ok | 21:39 |
| lkcl | then finally switch on the 12 v power | 21:39 |
| Las[m] | I don't think this has a power switch, though I may just not be missing it | 21:39 |
| lkcl | it doesn't. | 21:40 |
| Las[m] | It powered on automatically when I put the plug in too | 21:40 |
| lkcl | i mean the power switch at the mains which the 12v PSU is connected into | 21:40 |
| lkcl | then you didn't read my instructions carefully | 21:40 |
| lkcl | i said, *disconnect* the 12 v PSU entirely. | 21:40 |
| lkcl | that could have been a costly mistake | 21:40 |
| Las[m] | apparently yeah | 21:41 |
| lkcl | because as the 12v connector comes into contact with the pin and the outer ring, you get "transient spikes" | 21:41 |
| Las[m] | so I should be using a switch to avoid that, even if on the other end? | 21:41 |
| lkcl | by disconnecting the PSU, when you plug it back on, it delivers one single "smooth" uplift of 12 v power | 21:41 |
| lkcl | without any spikes. | 21:42 |
| lkcl | yes, really. | 21:42 |
| lkcl | realistically | 21:42 |
| lkcl | plus, because you're putting quite a bit of force on the connector, if you slip it will put 12 v power onto random components | 21:42 |
| lkcl | so, anyway, you should be good to go. | 21:43 |
| lkcl | as in, re-run the openocd command | 21:43 |
| lkcl | or the "make upload" thing | 21:43 |
| Las[m] | Putting the plug into the FPGA, after switching off the PSU, made it light on the FPGA for ~100 ms | 21:44 |
| Las[m] | Is this problematic? | 21:44 |
| Las[m] | oh, it worked | 21:45 |
| lkcl | that's just the capacitors in the PSU discharging | 21:45 |
| lkcl | hurrah | 21:46 |
| cesar | yay! | 21:46 |
| Las[m] | The blinking pattern is different, is this a feature of Libre-SOC or Litex or whatever? | 21:46 |
| lkcl | ok now you should be able to run minicom -D /dev/ttyUSB0 | 21:46 |
| lkcl | or maybe /dev/ttyUSB1 | 21:46 |
| lkcl | and connect to the serial console | 21:46 |
| lkcl | ls -altr /dev/ttyUSB* first to find out what the name is | 21:46 |
| Las[m] | it seems to be /dev/ttyUSB1 | 21:47 |
| Las[m] | but it doesn't show anything related to Libre-SOC...? | 21:47 |
| lkcl | excellent, run minicom -D /dev/ttyUSB1 | 21:47 |
| lkcl | it should be running the litex bios at this point | 21:47 |
| lkcl | you might need to reset it (re-run the FPGA upload) to catch it in the act of printing out BIOS messages to the serial console | 21:48 |
| Las[m] | In the bottom it says "... | Offline | ttyUSB1" | 21:48 |
| lkcl | if it's showing anything *at all* that's a good sign | 21:48 |
| lkcl | ah you might need to configure it... | 21:48 |
| Las[m] | yep, I can see it now | 21:48 |
| Las[m] | I have a `litex` prompt but I can't input anything | 21:49 |
| Las[m] | "- bus errors: 2/256" | 21:49 |
| Las[m] | "- addr errors: 32/8192" | 21:49 |
| lkcl | whahey! | 21:49 |
| lkcl | you've got something *at all* | 21:49 |
| lkcl | that's a fantastic sign | 21:49 |
| Las[m] | "- data errors: 524279/524288" | 21:50 |
| lkcl | GREAT | 21:50 |
| Las[m] | Are the errors me having broken the FPGA or an issue with Libre-SOC, or is that not knowable? | 21:50 |
| lkcl | that means it actually tried to even test the DDR3 RAM | 21:50 |
| lkcl | which is itself a fantastic sign | 21:50 |
| Las[m] | `SDRAM: 131072KiB 16-bit @ 220Mbps/pin` | 21:50 |
| lkcl | the fact that it's reporting that at all is amazing | 21:51 |
| Las[m] | You didn't expect this to work? | 21:51 |
| lkcl | of course not! :) | 21:51 |
| Las[m] | I don't know what I would have done if it didn't work lol | 21:51 |
| Las[m] | I've already spent so much time on this | 21:51 |
| lkcl | this stuff is a total pain in the ass, any success is amazing | 21:51 |
| lkcl | initialisation of DRAM is pretty hit-and-miss | 21:52 |
| Las[m] | Is there any chance of me being able to test some PPC software, or is that impossible? | 21:52 |
| Las[m] | s/software/assembly | 21:52 |
| lkcl | it's timing related and has to be hardcoded depending on the config | 21:52 |
| Las[m] | or is there a test suite I could run? | 21:52 |
| lkcl | weeelll... in a few months, maybe | 21:52 |
| lkcl | we're at the "bare metal" stage at the moment | 21:53 |
| lkcl | there's no MMU, no L1 cache yet. | 21:53 |
| lkcl | so you can't run linux | 21:53 |
| Las[m] | well yeah I could guess that | 21:53 |
| lkcl | but you are basically already *running* ppc software | 21:53 |
| lkcl | that BIOS was compiled with the compiler you added in to libresoc-litex a couple days ago | 21:54 |
| Las[m] | ah really? | 21:54 |
| Las[m] | Ah | 21:54 |
| Las[m] | well that's pretty nice | 21:54 |
| lkcl | yeah | 21:54 |
| lkcl | like i said, it's pretty amazing success | 21:55 |
| lkcl | but that BIOS is a bare-metal application | 21:55 |
| Las[m] | is it expected that I can't input anything? | 21:55 |
| lkcl | a bit like programming an arduino or an embedded STM32F | 21:55 |
| lkcl | sigh, long story, that one | 21:55 |
| lkcl | the version of litex i am using - you upgraded remember - uses "polling" of the litex UART | 21:56 |
| lkcl | there was a fight between Raptor Engineering and Florent | 21:56 |
| Las[m] | `tio` works better | 21:56 |
| lkcl | who refused to accept patches to the interrupt system | 21:56 |
| Las[m] | I can at least press enter | 21:56 |
| lkcl | that's a really good sign | 21:57 |
| Las[m] | it says "Command not found" even! | 21:57 |
| lkcl | briiillliant | 21:57 |
| lkcl | that's because there's no commands been compiled in for that (very early) litex bios | 21:57 |
| lkcl | upgrading right now isn't recommended | 21:57 |
| lkcl | because the interrupt mechanism has changed | 21:58 |
| lkcl | and the build (libresoc-litex) has to be aware of that | 21:58 |
| Las[m] | You're going to try updating the version of LiteX you're using? | 21:58 |
| lkcl | not unless or until i absolutely need to | 21:58 |
| lkcl | and like i said a couple days ago, the focus is on the core at the moment | 21:59 |
| lkcl | there are two priority tasks: | 21:59 |
| lkcl | 1) get the pieces in place for SIMD back-end ALUs | 21:59 |
| lkcl | 2) get the MMU and L1 cache working, and (Cesar) the LD/ST Exception mechanism | 22:00 |
| Las[m] | Sounds great | 22:00 |
| lkcl | when we have the MMU unit tests running successfully *then* it is worthwhile considering getting litex up and running with it | 22:01 |
| Las[m] | Hopefully I can get a Libre-SOC ASIC in 2025 | 22:01 |
| Las[m] | or was it 2023? | 22:02 |
| Las[m] | I think next I'll try getting the entire ASIC build process working, since there's very little left for that. | 22:02 |
| lkcl | we've got to get an NGI POINTER single-core done in 2022 | 22:02 |
| Las[m] | After that I'll try getting the tests for Libre-SOC working, so you can have CI | 22:02 |
| Las[m] | is that the router thing? | 22:02 |
| lkcl | star | 22:02 |
| lkcl | yes | 22:03 |
| Las[m] | Hopefully I can buy it in 2022 then! | 22:03 |
| lkcl | although if it's practial and there's time i'd like to Mux in Richard Herveille's RGB/TTL code | 22:03 |
| Las[m] | Or make my own possibly! | 22:03 |
| lkcl | it'll be a test ASIC, about 160 made | 22:03 |
| lkcl | @ USD 30,000 - 40,000 for those 160 ASICs | 22:04 |
| Las[m] | Not that expensive TBH | 22:04 |
| lkcl | exactly | 22:04 |
| lkcl | 360nm, through Staf Verhaegen's Chips4Makers[m], is only EUR 1750 | 22:04 |
| lkcl | and that's i think 20 ASICs? | 22:05 |
| Las[m] | I have to package that too actually | 22:05 |
| lkcl | 50 | 22:05 |
| lkcl | https://chips4makers.io/ | 22:05 |
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