| lkcl | huhn. set 70 mhz and it still ran. | 11:49 |
|---|---|---|
| lkcl | to "believe" this i'm going to have to push things so that it breaks (instructions stop working entirely) | 11:49 |
| lkcl | trying 100 mhz | 11:50 |
| lkcl | holy cow it's still runnable at 100 mhz | 12:06 |
| lkcl | i'm going to have to try 200 | 12:06 |
| lkcl | i need to find a point where "breakage" occurs in order to confirm that it's genuinely running at this speed | 12:07 |
| markos | 100Mhz!! | 12:38 |
| markos | that's actually usable to test SPV64 instructions live! | 12:39 |
| markos | what's the FPGA setup you're using? | 12:39 |
| markos | ie, is it something easy to replicate? | 12:39 |
| lkcl | nmigen. | 12:46 |
| lkcl | $ python3 src/ls2.py versa_ecp5 ./coldboot/coldboot.bin | 12:46 |
| lkcl | i haven't documented the other repos needed yet (opencores uart16550, libgram, etc) | 12:47 |
| lkcl | ok finally i'm starting to get "negative timing budgets" at 200 mhz :) | 12:47 |
| lkcl | yay that didn't work | 12:47 |
| lkcl | so, holy cow, the 100 mhz is genuine | 12:48 |
| lkcl | using a VERSA_ECP5 at the moment | 12:48 |
| lkcl | okaay it's intermittent success | 13:10 |
| lkcl | one build works, the next doesn't | 13:10 |
| markos | amazing | 13:12 |
| lkcl | am trying 70 mhz | 13:13 |
| lkcl | reaally need this DDR3 Controller functional so i can move on | 13:13 |
| lkcl | at least, thank goodness, i am above the threshold where the DDR3 IC stops working altogether (48-55 mhz) | 13:14 |
| octavius | "one build works, the next doesn't", that reminds of my previous job. One of my colleagues, an FPGA engineer had the exact same kind of cycle...especially given that the internal blocks were poorly documented XD | 23:39 |
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