Saturday, 2022-02-26

lkclhuhn. set 70 mhz and it still ran.11:49
lkclto "believe" this i'm going to have to push things so that it breaks (instructions stop working entirely)11:49
lkcltrying 100 mhz11:50
lkclholy cow it's still runnable at 100 mhz12:06
lkcli'm going to have to try 20012:06
lkcli need to find a point where "breakage" occurs in order to confirm that it's genuinely running at this speed12:07
markosthat's actually usable to test SPV64 instructions live!12:39
markoswhat's the FPGA setup you're using?12:39
markosie, is it something easy to replicate?12:39
lkcl$ python3 src/ versa_ecp5 ./coldboot/coldboot.bin12:46
lkcli haven't documented the other repos needed yet (opencores uart16550, libgram, etc)12:47
lkclok finally i'm starting to get "negative timing budgets" at 200 mhz :)12:47
lkclyay that didn't work12:47
lkclso, holy cow, the 100 mhz is genuine12:48
lkclusing a VERSA_ECP5 at the moment12:48
lkclokaay it's intermittent success13:10
lkclone build works, the next doesn't13:10
lkclam trying 70 mhz13:13
lkclreaally need this DDR3 Controller functional so i can move on13:13
lkclat least, thank goodness, i am above the threshold where the DDR3 IC stops working altogether (48-55 mhz)13:14
octavius"one build works, the next doesn't", that reminds of my previous job. One of my colleagues, an FPGA engineer had the exact same kind of cycle...especially given that the internal blocks were poorly documented XD23:39

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