| lkcl | yehyeh, routing is done randomly (as in, literally, you apply a randomisation algorithm to select routing connections, and then "improve" it by picking another one, and seeing if the timing is better than the previous one. repeat) | 03:42 |
|---|---|---|
| lkcl | programmerjake, i'm getting shift_rot errors with grev., didn't we remove Rc=1? | 19:33 |
| lkcl | AssertionError: 8 != 2 : CR0 .4byte 0x1464292d # grev. 3, 4, 5 | 19:33 |
| programmerjake | no...that was with ternlog | 19:35 |
| programmerjake | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/bitmanip.mdwn;h=b2b0ad8b638d35ad966410d31365f963f5acbee8;hb=HEAD#l27 | 19:35 |
| programmerjake | iirc i discovered the list of Rc=1 workarounds and added grev to it | 19:36 |
| programmerjake | https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_decoder2.py;hb=c0380bd02b26a967221f7dc13f632637aae3d144#l587 | 19:37 |
| programmerjake | essentially that Case is a replacement for the csv column that we never added | 19:40 |
| programmerjake | which git commits are you on? | 19:40 |
| programmerjake | which test .py are you running? | 19:42 |
| lkcl | latest. | 19:42 |
| lkcl | shift_rot test_pipe_caller | 19:42 |
| programmerjake | hmm...lemme test it | 19:43 |
| programmerjake | well, reading your changes, i think i found the problem: | 19:47 |
| programmerjake | https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/shift_rot/main_stage.py;h=df8b17c23eacd2f62d9696ac37b1c83ca9104edf;hb=a36539e789f37f6f385ef719684fbf04c0036d91#l52 | 19:47 |
| programmerjake | (64).bit_length() == 7 not 6. you need log2 not bit_length | 19:47 |
| lkcl | or just -1 | 19:48 |
| lkcl | well spotted | 19:48 |
| programmerjake | i'd just call an int log2 function | 19:48 |
| lkcl | actually... it's (XLEN-1).bit_length() | 19:50 |
| programmerjake | depends on if you want floor(log2(v)) or ceil(log2(v)) | 19:50 |
| programmerjake | just call https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/helpers.py;hb=c0380bd02b26a967221f7dc13f632637aae3d144#l363 | 19:51 |
| lkcl | i'm testing making the regfiles and pipelines 32-bit, it gets a 40% reduction in size, that's without trying anything fancy with the L1 caches | 19:52 |
| lkcl | or LDST | 19:52 |
| lkcl | sorted and moving on. | 19:52 |
| programmerjake | it asserts the input is a power of 2 so we don't have to decide between floor/ceil | 19:52 |
| programmerjake | :) | 19:52 |
| lkcl | am waiting for microwatt to build for ulx3s. 3h40m so far. | 19:53 |
| lkcl | mental | 19:53 |
| programmerjake | fun... | 19:54 |
| programmerjake | did the test pass now? | 19:54 |
| lkcl | yes, all good - thank you for investigating | 20:38 |
| programmerjake | :) | 20:39 |
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