Sunday, 2022-02-27

lkclyehyeh, routing is done randomly (as in, literally, you apply a randomisation algorithm to select routing connections, and then "improve" it by picking another one, and seeing if the timing is better than the previous one. repeat)03:42
lkclprogrammerjake, i'm getting shift_rot errors with grev., didn't we remove Rc=1?19:33
lkclAssertionError: 8 != 2 : CR0 .4byte 0x1464292d # grev. 3, 4, 519:33
programmerjakeno...that was with ternlog19:35
programmerjakeiirc i discovered the list of Rc=1 workarounds and added grev to it19:36
programmerjakeessentially that Case is a replacement for the csv column that we never added19:40
programmerjakewhich git commits are you on?19:40
programmerjakewhich test .py are you running?19:42
lkclshift_rot test_pipe_caller19:42
programmerjakehmm...lemme test it19:43
programmerjakewell, reading your changes, i think i found the problem:19:47
programmerjake(64).bit_length() == 7 not 6. you need log2 not bit_length19:47
lkclor just -119:48
lkclwell spotted19:48
programmerjakei'd just call an int log2 function19:48
lkclactually... it's (XLEN-1).bit_length()19:50
programmerjakedepends on if you want floor(log2(v)) or ceil(log2(v))19:50
programmerjakejust call;a=blob;f=src/openpower/decoder/;hb=c0380bd02b26a967221f7dc13f632637aae3d144#l36319:51
lkcli'm testing making the regfiles and pipelines 32-bit, it gets a 40% reduction in size, that's without trying anything fancy with the L1 caches19:52
lkclor LDST19:52
lkclsorted and moving on.19:52
programmerjakeit asserts the input is a power of 2 so we don't have to decide between floor/ceil19:52
lkclam waiting for microwatt to build for ulx3s. 3h40m so far.19:53
programmerjakedid the test pass now?19:54
lkclyes, all good - thank you for investigating20:38

Generated by 2.17.1 by Marius Gedminas - find it at!